Battery cell monitoring and balancing circuit

• US 7,081,737 B2
• Filed: 06/19/2003
• Issued: 07/25/2006
• Est. Priority Date: 06/19/2003
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Li, Guoxing, Liu, Liusheng
• Primary Examiner(s): TIBBITS, PIA FLORENCE
• Application Number:
  US10/464,973
• Publication Number:
  US 20040257042A1
• Time in Patent Office: 1,132 Days
• Field of Search: 320/130, 320/106, 320/116, 320/122, 320/128, 320/135, 340/636.15, 341/155
• US Class Current: 320/130
• CPC Class Codes: H01M 10/441 for several batteries or cells simultaneously or sequentially
• CPC Class Codes: H02J 7/0018 using separate charge circuits
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A monitoring circuit for accurately monitoring a voltage level from each of a plurality of battery cells of a battery pack includes an analog to digital converter (ADC) and a processor. The ADC is configured to accept an analog voltage signal from each of the plurality of battery cells and convert each analog voltage signal to a digital signal representative of an accurate voltage level of each battery cell. The processor receives such signals and provides a safety alert signal based on at least one of the signals. The ADC resolution may be adjustable. A balancing circuit provides a balancing signal if at least two of the digital signals indicate a voltage difference between two cells is greater than a battery cell balance threshold. An electronic device including such monitoring and balancing circuits is also provided. Various methods are also provided.

Claims

1. A balancing circuit comprising:

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of a plurality of battery cells of a battery pack and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell;

a processor configured to receive each said digital signal and to provide a balance signal if at least two of said digital signals are representative of a voltage difference between a first voltage level of a first battery cell and a second voltage level of a second battery cell greater than a battery cell balance threshold;

a switch network coupled between said battery pack and said ADC, said processor controlling said switch network to enable said ADC to directly sample said analog voltage signal from each of said plurality of battery cells; and

a bleeding network circuit configured to accept said balance signal and provide a bleeding current to one of said plurality of battery cells in response to said balance signal wherein said bleeding network circuit provides a first bleeding current to said second battery cell if said second voltage level of said second battery cell is greater than said first voltage level of said first battery cell, said bleeding network circuit applying said first bleeding current for a first time interval to reduce said second voltage level to a level substantially equal to said first voltage level.

2. The balancing circuit of claim 1, wherein a third battery cell has a third voltage level, said third voltage level greater than said first voltage level, said third voltage level greater than said second voltage level, said bleeding network circuit applying said first bleeding current to said third battery cell for a second time interval to reduce said third voltage level to said level substantially equal to said first voltage level, wherein at least some portion of said first time interval and said second time interval overlap.

3. The balancing circuit of claim 2, wherein said first time interval has a first starting time and said second time interval has a second starting time, said first starting time substantially equal to said second starting time and wherein said second time interval is longer than said first time interval.

4. The balancing circuit of claim 1, wherein said first bleeding current provided by said bleeding network circuit is adjustable in response to said balance signal from said processor.

5. The balancing circuit of claim 4, wherein a third battery cell has a third voltage level, and wherein said second voltage level is greater than said first voltage level by a first difference level, and said third voltage level is greater than said first voltage level by a second difference level, and wherein said second difference level is greater than said first difference level, and wherein said bleeding network circuit provides said first bleeding current to said second battery cell and a second bleeding current to said third battery cell, said second bleeding current greater than said first bleeding current.

8. The balancing circuit of claim 1, wherein said balance signal is also provided to a charge shuttling circuit configured to shuffle charges among said plurality of battery cells in response to said balance signal.

9. The balancing circuit of claim 8, wherein said charge shuttling circuit is configured to shuttle charges from said second battery cell to said first battery cell if said second voltage level is greater than said first voltage level.

10. The balancing circuit of claim 8, wherein said charge shuttling circuit comprises an energy storage element.

12. The balancing circuit of claim 1, wherein said balance signal is provided when said battery pack is in a discharge mode.

13. The balancing circuit of claim 1, wherein said ADC is an averaging type ADC.

14. The balancing circuit of claim 1, wherein said ADC has a resolution, and said resolution is adjustable by said processor.

6. A balancing circuit comprising:

an analog to digital converter (ADC) configured to accept an analog voltage signal from each of a plurality of battery cells of a battery pack and convert each said analog voltage signal to a digital signal representative of a voltage level of each said battery cell;

a processor configured to receive each said digital signal and to provide a balance signal if at least two of said digital signals are representative of a voltage difference between a first voltage level of a first battery cell and a second voltage level of a second battery cell greater than a battery cell balance threshold;

a bleeding network circuit configured to accept said balance signal and provide a bleeding current to one of said plurality of battery cells in response to said balance signal, said bleeding current being adjustable in response to said balance signal from said processor;

wherein said bleeding network circuit comprises a plurality of bleeding circuits associated with each said plurality of battery cells, at least one of said plurality of bleeding circuits comprising;

a first switch having a first resistive element coupled to a terminal of said first switch, said first resistive element having a first resistive value; and

a second switch having a second resistive element coupled to a terminal of said second switch, said second resistive element having a second resistive value, said second resistive value less than said first resistive value.

7. The balancing circuit of claim 6, wherein a first bleeding current is applied to an associated battery cell if said first switch is ON and said second switch is OFF, and a second bleeding current is applied to said associated battery cell if said first switch if OFF and said second switch if ON, wherein said second bleeding current is greater than said first bleeding current.

11. The balancing circuit of violin 10, wherein said energy storage element comprises a capacitor.