Ferroelectric memory input/output apparatus

• US 7,082,047 B2
• Filed: 04/18/2005
• Issued: 07/25/2006
• Est. Priority Date: 12/03/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chow, David GenLong
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US11/109,197
• Publication Number:
  US 20050185443A1
• Time in Patent Office: 463 Days
• Field of Search: 365/145, 365/149, 365/185.04, 365/185.18
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.

Claims

1. A memory system, comprising:

device control circuitry to receive a control signal and to assert the control signal; and

at least two ferroelectric polymer memory devices arranged such that a first memory device receives the control signal from the device control circuitry and a control signal output from the first memory device is electrically connected to a control signal input to a sequential device, such that the control signal is asserted at the devices in series and the devices have busy signal to indicate when the devices are responding to the control signal.

2. The memory system of claim 1, wherein each memory device further comprises a address latch and a data latch, operable to temporarily hold address and data signals.

3. The memory system of claim 1, the memory system further comprising a data bus to transfer data between each memory device and the device control circuitry.

4. The memory system of claim 1, the memory system further comprising an address bus to provide addressing of the memory devices.

5. The memory system of claim 1, the device control circuitry and at least two memory arrays residing on a memory card.

6. The memory system of claim 5, the memory arrays on the memory card being to act as a single block of memory.