Non-volatile latch with magnetic junctions
First Claim
1. A memory storage circuit, comprising:
- a plurality of magnetic elements each configured to store bits in a first logic state or a second logic state;
a plurality of transistors coupled to at least two of the magnetic elements, wherein the plurality of transistors are collectively configured to store bits in the first and second logic states;
a first set of circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors, wherein the first set of circuitry comprises a first set of conductive structures configured to pass current through the set of magnetic elements; and
a second set of circuitry configured to program the set of magnetic elements, wherein the second set of circuitry comprises;
a second set of conductive structures configured to induce respective magnetic fields about each of the set of magnetic elements; and
a program transistor coupled between the set of magnetic elements and configured to enable current flow among the second set of conductive structures.
6 Assignments
0 Petitions
Accused Products
Abstract
A memory storage circuit is provided which includes a plurality of magnetic elements each configured to store bits in a first or a second logic state. The storage circuit may further include a plurality of transistors coupled to at least two of the magnetic elements. Such a plurality of transistors may be collectively configured to store bits in the first and second logic states as well. The memory storage circuit may include circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors. Another circuit is provided which includes a magnetic element interposed between a bit line and an electrode. The circuit may further include a first set of circuitry configured to induce current flow through the magnetic element in a direction from the electrode to the bit line. A method for operating a memory storage circuit with the aforementioned configurations is also provided.
33 Citations
15 Claims
-
1. A memory storage circuit, comprising:
-
a plurality of magnetic elements each configured to store bits in a first logic state or a second logic state; a plurality of transistors coupled to at least two of the magnetic elements, wherein the plurality of transistors are collectively configured to store bits in the first and second logic states; a first set of circuitry configured to load bits from a set of the magnetic elements into the plurality of transistors, wherein the first set of circuitry comprises a first set of conductive structures configured to pass current through the set of magnetic elements; and a second set of circuitry configured to program the set of magnetic elements, wherein the second set of circuitry comprises; a second set of conductive structures configured to induce respective magnetic fields about each of the set of magnetic elements; and a program transistor coupled between the set of magnetic elements and configured to enable current flow among the second set of conductive structures. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A circuit, comprising:
-
a pair of magnetic elements respectively configured to store bits of opposing logic states, wherein each of the a-magnetic elements is interposed between a respective bit line and a respective electrode; a plurality of transistors coupled to the pair of magnetic elements which are collectively configured to store bits of opposing logic states; a first node interposed between the plurality of transistors and a respective electrode of one of the pair of magnetic elements; a second node interposed between the plurality of transistors and a respective electrode of the other of the pair of magnetic elements; and a first set of circuitry configured to load bits from the pair of magnetic elements to the plurality of transistors by inducing current flow through each of the pair of magnetic elements in a direction from their respective electrodes to their respective bit lines. - View Dependent Claims (11, 12)
-
-
13. A method for operating a latch, comprising:
-
charging up first and second nodes of a volatile portion of the latch, wherein the first and second nodes are respectively arranged at opposing ends of the volatile portion; inducing current flow through two magnetic elements respectively arranged within first and second regions of a non-volatile portion of the latch, wherein the first and second regions are respectively arranged in alignment with the opposing ends of the volatile portion, and wherein the current flow is directed from electrodes respectively arranged adjacent to the two magnetic elements to bit lines respectively arranged on sides of the two magnetic elements opposing the electrodes; and loading the first and second nodes to have logic states which correspond to resistance levels within the magnetic elements in the first and second regions, respectively. - View Dependent Claims (14, 15)
-
Specification