Adaptive radio transceiver with CMOS offset PLL

• US 7,082,293 B1
• Filed: 10/27/2000
• Issued: 07/25/2006
• Est. Priority Date: 10/21/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pan, Meng-An, Rofougaran, Maryam, Chien, Hung-Ming, Rael, Jacob, Rofougaran, Ahmadreza, Wu, Stephen, Ibrahim, Brima, Syed, Masood
• Primary Examiner(s): Milord, Marceau
• Application Number:
  US09/698,498
• Time in Patent Office: 2,097 Days
• Field of Search: 455/260, 455/76, 455/77, 455/84, 455/85, 455/86, 455/87, 455/115.1, 455/180.3, 455/190.1, 455/192.1, 455/207, 455/208, 455/209, 455/264, 455/20
• US Class Current: 455/260
• CPC Class Codes: H03L 2207/12 Indirect frequency synthesis using a mixer in the phase-locked loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/713 using frequency hopping
• CPC Class Codes: H04B 17/101 for measurement of specific parameters of the transmitter or components thereof
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/19 Self-testing arrangements
• CPC Class Codes: H04B 17/20 of receivers

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A complimentary metal oxide semiconductor (CMOS) phase lock loop, comprising:

an oscillator having a tuning input, and an output with a tunable frequency responsive to the tuning input;

a mixer to mix the oscillator output with a second signal to produce a mixed signal; and

a phase detector outputting an error signal which is a function of a phase difference between the mixed signal and an input signal, the error signal being applied to the tuning input,

wherein the oscillator comprises a voltage controlled oscillator, the tuning input being responsive to a voltage of the error signal, the CMOS phase lock loop further comprising a bandpass filter to filter the mixed signal before being applied to the phase detector, the filtered mixed signal comprising a difference frequency between the tuned frequency of the oscillator output and a frequency of the second signal, a limiter to limit the filtered mixed signal from the filter before being applied to the phase detector, a charge pump disposed between the phase detector and the oscillator, and a loop filter disposed between the charge pump and the oscillator.

2. The CMOS phase lock loop according to claim 1, wherein the CMOS phase lock loop is integrated onto a single integrated circuit (IC) chip.

3. The CMOS phase lock loop according to claim 1, wherein the input signal comprises a transmitter intermediate frequency (IF) input signal.

4. The CMOS phase lock loop according to claim 1, wherein the oscillator is an off-chip oscillator.

5. The CMOS phase lock loop according to claim 1, wherein the mixer operates at a lower clock frequency than the voltage controlled oscillator.

6. The CMOS phase lock loop according to claim 1, wherein the CMOS phase lock loop is used with a transmitter in a wireless communication device.

7. The CMOS phase lock loop according to claim 1, wherein the CMOS phase lock loop is part of a wireless communication device.

8. The CMOS phase lock loop according to claim 7, wherein the wireless communication device supports communications using orthogonal frequency division multiplexing.

9. The CMOS phase lock loop according to claim 7, wherein the wireless communication device supports communications using spread spectrum modulation.

10. The CMOS phase lock loop according to claim 7, wherein the wireless communication device supports communications using frequency hopping.

11. The CMOS phase lock loop according to claim 7, wherein the wireless communication device supports communications using direct sequence spread spectrum modulation.

12. A complimentary metal oxide semiconductor (CMOS) phase lock loop, comprising:

oscillator means for generating a first signal having a tunable frequency, the oscillating means comprising tuning means for tuning the frequency of the first signal;

mixer means for mixing the first signal with a second signal to produce a mixed signal; and

detector means for detecting a phase difference between the mixed signal and an input signal, and generating an error signal which is a function of the phase difference, the tuning means being responsive to the error signal,

wherein the oscillator means comprises a voltage controlled oscillator, the tuning means being responsive to a voltage of the error signal, the CMOS phase lock loop further comprising filter means for filtering the mixed signal before being applied to the detector means, the filtered mixed signal comprising a difference frequency between the tuned frequency of the first signal and a frequency of the second signal, means for limiting the filtered mixed signal from the filter means before being applied to the detector means, current means for sourcing current to the tuning means responsive to the error signal, and means for filtering the current sourced error signal from the current means before being applied to the tuning means.

13. The CMOS phase lock loop according to claim 12, wherein the CMOS phase lock loop is integrated onto a single integrated circuit (IC) chip.

14. The CMOS phase lock loop according to claim 12, wherein the input signal comprises a transmitter intermediate frequency (IF) input signal.

15. The CMOS phase lock loop according to claim 12, wherein the oscillator means is an off-chip oscillator means.

16. The CMOS phase lock loop according to claim 12, wherein the mixer means operates at a lower clock frequency than the voltage controlled oscillator.

17. The CMOS phase lock loop according to claim 12, wherein the CMOS phase lock loop is used with a transmitter in a wireless communication device.

18. The CMOS phase lock loop according to claim 12, wherein the CMOS phase lock loop is part of a wireless communication device.

19. The CMOS phase lock loop according to claim 18, wherein the wireless communication device supports communications using orthogonal frequency division multiplexing.

20. The CMOS phase lock loop according to claim 18, wherein the wireless communication device supports communications using spread spectrum modulation.

21. The CMOS phase lock loop according to claim 18, wherein the wireless communication device supports communications using frequency hopping.

22. The CMOS phase lock loop according to claim 18, wherein the wireless communication device supports communications using direct sequence spread spectrum modulation.