Automated analysis of RTL code containing ASIC vendor rules

• US 7,082,584 B2
• Filed: 04/30/2003
• Issued: 07/25/2006
• Est. Priority Date: 04/30/2003
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Fry, Randall P., Pierce, Gregory A., Balasubramanian, Balamurugan, Chaturvedula, Kavitha, Lahner, Juergen, Adusumalli, Srinivas, Atmakuri, Kiran, Devineni, Krishna
• Primary Examiner(s): Thompson, A. M.
• Assistant Examiner(s): LAM, NELSON C
• Application Number:
  US10/427,609
• Publication Number:
  US 20040221249A1
• Time in Patent Office: 1,182 Days
• Field of Search: 716/4, 716/1, 716/18, 716/5
• US Class Current: 716/102
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.

Claims

1. A method of automatically analyzing RTL code comprising steps of:

(a) receiving as input RTL code for an integrated circuit design;

(b) selecting an RTL platform incorporating design rules for a vendor of the integrated circuit design;

(c) displaying the design rules from the RTL platform on a graphic user interface;

(d) selecting a number of the design rules from the graphic user interface for analyzing the RTL code;

(e) performing an analysis in the RTL platform of the RTL code for each of the selected design rules; and

(f) generating as output a result of the analysis for each of the selected design rules wherein step (d) further includes selecting one of a severity level and a threshold value for at least one of the selected design rules from the graphic user interface.

2. The method of claim 1 wherein the design rules selected from the graphic user interface include detecting and identifying a possible RTL coding problem consisting of at least one of missing clock information, unconstrained I/O, critical paths, time budgeting, large structures, local congestion, unused ports, floating pins, global congestion, latches, unregistered I/O, high fan-out nets, shift registers, logic depth, clock domain crossings, gate explosion, resource sharing, use of casex/casez, incomplete case statements, critical multiplexer structures, gated reset, asynchronous/combinational loops, multiple driven nets, logical cone fan-in, logical cone fan-out, and large arithmetic operators.

3. A computer program product for automatically analyzing RTL code comprising:

a medium for embodying a computer program for input to a computer; and

a computer program embodied in the medium for causing the computer to perform steps of;

(a) receiving as input RTL code for an integrated circuit design;

(b) selecting an RTL platform incorporating design rules for a vendor of the integrated circuit design;

(c) displaying the design rules from the RTL platform on a graphic user interface;

(d) selecting a number of the design rules from the graphic user interface for analyzing the RTL code;

(e) performing an analysis in the RTL platform of the RTL code for each of the selected design rules; and

(f) generating as output a result of the analysis for each of the selected design rules wherein step (d) further includes selecting one of a severity level and a threshold value for at least one of the selected design rules from the graphic user interface.

4. The computer program product of claim 3 wherein the design rules selected from the graphic user interface include detecting and identifying a possible RTL coding problem consisting of at least one of missing clock information, unconstrained I/O, critical paths, time budgeting, large structures, local congestion, unused ports, floating pins, global congestion, latches, unregistered I/O, high fan-out nets, shift registers, logic depth, clock domain crossings, gate explosion, resource sharing, use of casex/casez, incomplete case statements, critical multiplexer structures, gated reset, asynchronous/combinational loops, multiple driven nets, logical cone fan-in, logical cone fan-out, and large arithmetic operators.