Method of estimating path delays in an IC
First Claim
1. A method for generating path delay data representing an estimated signal path delay through each of a plurality of signal paths within an integrated circuit (IC), wherein the IC includes a plurality of cells and a plurality of nets for conveying signals between the cells, the method comprising the steps of:
- a. selecting one of the nets;
b. reading RC extraction data indicating an estimated impedance of each section of the net selected at step a from a database storing RC extraction data indicating an estimated impedance of each section of each of the plurality of nets, and computing as a function of the read RC extraction data, an estimated path delay through each section of the net selected at step a that is included in at least one of the plurality of signal paths; and
c. adjusting the path delay data for each one of the plurality of signal paths that includes a section of the net selected at step a by incrementing an estimated signal path delay that the path delay data represents by an amount of the estimated path delay through that section of the net computed at step b.
1 Assignment
0 Petitions
Accused Products
Abstract
To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.
27 Citations
16 Claims
-
1. A method for generating path delay data representing an estimated signal path delay through each of a plurality of signal paths within an integrated circuit (IC), wherein the IC includes a plurality of cells and a plurality of nets for conveying signals between the cells, the method comprising the steps of:
-
a. selecting one of the nets; b. reading RC extraction data indicating an estimated impedance of each section of the net selected at step a from a database storing RC extraction data indicating an estimated impedance of each section of each of the plurality of nets, and computing as a function of the read RC extraction data, an estimated path delay through each section of the net selected at step a that is included in at least one of the plurality of signal paths; and c. adjusting the path delay data for each one of the plurality of signal paths that includes a section of the net selected at step a by incrementing an estimated signal path delay that the path delay data represents by an amount of the estimated path delay through that section of the net computed at step b. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. Computer readable media storing software which when read and executed by a computer, causes the computer to carry out a method for generating path delay data representing an estimated signal path delay through each of a plurality of signal paths within an integrated circuit (IC), wherein the IC includes a plurality of cells and a plurality of nets for conveying signals between the cells, wherein the method comprises the steps of:
-
a. selecting one of the nets, b. reading RC extraction data indicating an estimated impedance of each section of the net selected at step a from a database storing RC extraction data indicating an estimating impedance of each section of each of the plurality of nets, and computing as a function of the read RC extraction data, an estimated path delay through each section of the net selected at step a that is included in at least one of the plurality of signal paths; and c. adjusting the path delay data for each one of the plurality of signal paths that includes a section of the net selected at step a by incrementing an estimated signal path delay that the path delay data represents by an amount of the estimated path delay through that section of the net computed at step b. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
-
Specification