Method and apparatus for exception handling in a multi-processing environment

• US 7,082,610 B2
• Filed: 06/02/2001
• Issued: 07/25/2006
• Est. Priority Date: 06/02/2001
• Status: Expired due to Term

• Current Assignee: Ericsson AB (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Redback Networks Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Lal, Sanjay
• Primary Examiner(s): Follansbee, John
• Assistant Examiner(s): PATEL, HARESH N
• Application Number:
  US09/873,038
• Publication Number:
  US 20020184292A1
• Time in Patent Office: 1,879 Days
• Field of Search: 709/289, 709/281, 709200-203, 709217-224, 714 10- 13, 712 10- 22, 712 28- 31, 712/244, 719/318, 719310-322, 710260-269, 717/100, 717/108, 717/104, 717/107
• US Class Current: 719/318
• CPC Class Codes: G06F 2209/481 Exception handling
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A method and apparatus for exception handling in a multi-processor environment are described. In an embodiment, a method for handling a number of exceptions within a processor in a multi-processing system includes receiving an exception within the processor, wherein each processor in the multi-processor system shares a same memory. The method also includes executing a number of instructions at an address within a common interrupt handling vector address space of the same memory. The number of instructions cause the processor to determine an identification of the processor based on a query that is internal to the processor. Additionally, the method includes modifying execution flow of the exception to execute an interrupt handler located within one of a number of different interrupt handling vector address spaces.

Claims

1. A method for handling exceptions in a multi-processor system, the method comprising:

receiving an exception within a processor which is one of a plurality of processors of the multi-processor system which is implemented within a control card of a network element for routine data in networks, wherein each of the plurality of processors in the multi-processor system shares a memory within the multi-processor system, wherein the memory includes a common interrupt handling vector address space shared by the plurality of the processors and a dedicated interrupt handling vector address space for each of the plurality of the processors, and

executing one or more instructions at an address associated with a type of the received exception within the common interrupt handling vector address space of the memory, wherein the one or more instructions cause the processor to modify based on an identification of the processor an execution flow of the received exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the processor,

wherein the plurality of processors includes a first processor and a second processor, the first processor executing a first operating system and the second processor executing a second operating system, the second operating system being different from the first operating systems and wherein the first processor along with the first operating system is configured to handle routine of data received within the network element and the second processor along with the second operating system is configured to handle provisioning and configuration of the network element;

wherein the first operating system is a real-time operating system handling the routing of data within the network element and the second operating system is a non real-time operating system handling the provisioning and configuration of the network element.

2. The method of claim 1, wherein the first operating systems is associated with a first dedicated interrupt handling vector address spaces associated with a the first processor, and wherein the second operating system is associated with a second dedicated interrupt handling vector address space associated with the second processor.

3. The method of claim 1, further comprising determining the identification of the first processor by reading a bit of a register within the first processor without having to access the memory.

4. The method of claim 3, wherein the register is part of a cache throttling register of the first processor, and wherein a dedicated bit of the register is used to indicate the identification of the first processor while at least a portion of remaining bits is used for cache throttling purposes.

5. The method of claim 3, wherein determining the identification of the first processor comprises:

communicating during an initialization of the first processor with a memory controller coupling the first and second processors and the memory to retrieve the identification of the first processor from the memory controller; and

storing the retrieved identification of the first processor in the register within the first processor.

6. The method of claim 1, wherein each entry of the common interrupt handling vector space is associated with a different type of exceptions of the multi-processor system, and wherein a result of executing the instructions in the common interrupt handling vector space and the identification of the first processor receiving the exception determine the dedicated interrupt handling vector space associated with the first processor.

7. The method of claim 6, further comprising:

determining a type of the exception received by the first processor;

determining an entry of the common interrupt handling vector space based on the determined type of the exception; and

executing the one or more instructions stored at the determined entry to determine the dedicated interrupt handling vector space associated with the first processor based on the identification of the first processor.

8. The method of claim 7, further comprising executing an interrupt service routine based on the determined entry of the dedicated interrupt handling vector space of the first processor to handle the exception.

9. The method of claim 5, wherein the memory controller includes a plurality of interfaces and each of the interfaces is coupled to one of the plurality of processors, and wherein when each of the processors is being initialized during an initialization period of the multi-processor system, each of the plurality of the processors transmits a signal via a respective interface to the memory controller to identify each processor.

10. The method of claim 9, wherein in response to the signal received from each processor, the memory controller stores an identification of each processor within the memory controller, such that the identification of each processor is queried from the memory controller during runtime without having to access the memory.

11. A system comprising:

a plurality of processors including a first processor and a second processor implemented within a control card of a network element for routing data for networks;

a memory that includes

a common exception handling vector address space shared by the plurality of processors, and

a plurality of exception handling vector address spaces each associated with each of the plurality of processors, including a first exception handling vector address space and a second exception handling vector address space associated with the first processor and second processor respectively;

a memory controller coupled to the memory and the plurality of processors, wherein the first processor is to execute a first operating system,

wherein the second processor is to execute a second operating system, the second processor to execute one or more instructions in the common exception handling vector address space upon receipt of an exception, wherein the one or more instructions cause the second processor to modify based on an identification of the second processor an execution flow of the exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the second processor,

wherein the second operating system is different from the first operating system, and wherein the first processor along with the first operating system is configured to handle routing of data received within the network element and the second processor along with the second operating system is configured to handle provisioning and configuration of the network element;

wherein the first operating system is a real-time operating system handling the routing of data within the network element and the second operating system is a non real-time operating system handling the provisioning and configuration of the network element.

12. The system of claim 11, wherein the second processor further comprises an internal register to determine the identification of the second processor by reading a bit within the internal register.

13. The system of claim 12, wherein the internal register is part of a cache throttling register of the second processor, and wherein a dedicated bit of the internal register is used to indicate the identification of the second processor while at least a portion of remaining bits are used for cache throttling purposes.

14. The system of claim 12, wherein the identification of the second processor is determined by

communicating during an initialization of the second processor with the memory controller to retrieve the identification of the second processor from the memory controller, and

storing the retrieved identification of the second processor in the internal register within the second processor.

15. A storage medium that provides instructions for handling exceptions within a multi-processor system, which when executed by a machine, causes the machine to perform operations comprising:

receiving an exception within a processor which is one of a plurality of processors of the multi-processor system which is implemented within a control card of a network element for routing data in networks, wherein each of the plurality of processors in the multi-processor system shares a memory within the multi-processor system, wherein the memory includes a common interrupt handling vector address space shared by the plurality of the processors and a dedicated interrupt handling vector address space for each of the plurality of the processors, and

executing one or more instructions at an address associated with a type of the received exception within the common interrupt handling vector address space of the memory, wherein the one or more instructions cause the processor to modify based on an identification of the processor an execution flow of the received exception to execute an interrupt handler located within a respective dedicated interrupt handling vector address spaces associated with the processor,

wherein the plurality of processors includes a first processor and a second processor, the first processor executing a first operating system and the second processor executing a second operating systems the second operating system being different from the first operating systems, and

wherein the first processor along with the first operating system is configured to handle routing of data received within the network element and the second processor along with the second operating system is configured to handle provisioning and configuration of the network element;

wherein the first operating system is a real-time operating system handling the routing of data within the network element and the second operating system is a non real-time operating system handling the provisioning and configuration of the network element.

16. A storage medium of claim 15, wherein each of the operating systems is associated with a dedicated interrupt handling vector address spaces associated with a processor executing the respective operating system.

17. A storage medium of claim 15, further comprising determining the identification of the processor by reading a bit of a register within the processor without having to access the memory.

18. A storage medium of claim 17, wherein the register is part of a cache throttling register of the processor, and wherein a dedicated bit of the register is used to indicate the identification of the processor while at least a portion of remaining bits of the register is used for cache throttling purposes.

19. A storage medium of claim 15, wherein determining the identification of the processor comprises:

communicating during an initialization of the processor with a memory controller coupling the processors and the memory to retrieve the identification of the processor from the memory controller; and

storing the retrieved identification of the processor in the register within the processor.

20. A storage medium of claim 15, wherein each entry of the common interrupt handling vector space is associated with a different type of exceptions of the multi-processor system, and wherein a result of executing the instructions in the common interrupt handling vector space and the identification of the processor receiving the exception determine the dedicated interrupt handling vector space associated with the processor.