Method of forming a non-volatile memory device having floating trap type memory cell

• US 7,084,030 B2
• Filed: 07/31/2003
• Issued: 08/01/2006
• Est. Priority Date: 08/09/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Shin, Wang-Chul, Choi, Jung-Dal, Lee, Chang-Hyun
• Primary Examiner(s): Kang, Donghee
• Application Number:
  US10/632,496
• Publication Number:
  US 20040023451A1
• Time in Patent Office: 1,097 Days
• Field of Search: 438257-258, 438263-265, 257/316, 257/324, 257/371, 257/548, 257500-512
• US Class Current: 438/257
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Claims

1. A method comprising:

forming a device isolation layer in a substrate to define a low voltage region, a high voltage region, and a cell array region therein;

forming a first gate insulating layer on the substrate in the low voltage region;

forming a second gate insulating layer on the substrate in the high voltage region;

forming a first conductive layer overlying the low voltage region and the high voltage region;

forming a triple layer on the first conductive layer and on the substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer; and

forming a second conductive layer on the triple layer.

2. The method of claim 1, flurther comprising:

forming the first gate insulating layer and the first conductive layer in the cell array region; and

removing the first conductive layer in the cell array region, thereby exposing the substrate in the cell array region.

3. The method of claim 1, wherein the second gate insulating layer is thicker than the first gate insulating layer.

4. A method comprising:

forming a device isolation layer in a substrate to define a high voltage region, a low voltage region, and a cell array region therein;

forming a first gate insulating layer on the substrate in the low voltage region;

forming a second gate insulating layer on the substrate in the high voltage region;

forming a first conductive layer on the first gate insulating layer and the second gate insulating layer;

forming a triple layer on the first conductive layer and the substrate in the cell array region, the triple layer including a tunneling insulation layer, a charge storage layer, and a blocking insulation layer;

forming a second conductive layer on the triple layer;

patterning the second conductive layer, the triple layer, the first conductive layer, the first gate insulating layer, and the second gate insulating layer to form a second gate pattern in the high voltage region, a first gate pattern in the low voltage region;

patterning the second conductive layer, the triple layer to form a cell gate pattern in the cell array region;

removing portions of the second conductive layer and the triple layer from the second gate pattern and from the first gate pattern to form butting regions that expose portions of the first conductive layer;

forming an interlayer insulating layer overlying the resulting structure;

patterning the interlayer insulating layer to form contact holes that expose portions of the butting regions; and

filling the contact holes with contact plugs.

5. The method of claim 4, further comprising:

forming the first gate insulating layer and the first conductive layer in the cell array region, and

removing the first conductive layer in the cell array region, thereby exposing the substrate in the cell array region.

6. The method of claim 4, wherein the substrate further includes a resistor region, the method further comprising:

forming the second gate insulating layer, the first conductive layer, the triple layer, and the second conductive layer on the resistor region;

patterning the second conductive layer, the triple layer, the first conductive layer, and the second gate insulating layer, thereby forming a resistor pattern in the resistor region;

removing the second conductive layer and the triple layer from the resistor pattern;

forming the interlayer insulating layer on the resistor pattern; and

forming a contact hole exposing a portion of the first conductive layer by patterning the interlayer insulating layer.

7. The method of claim 4, further comprising forming insulating spacers on sidewalls of the second gate patterns, the first gate patterns, and the cell gate patterns.

8. The method of claim 4, wherein forming the second conductive layer comprises stacking a conductive silicon layer and a conductive metal layer.

9. The method of claim 4, wherein the second gate insulating layer is thicker than the first gate insulating layer.

10. A method comprising:

providing a substrate that includes a low voltage region, a high voltage region, and a cell array region;

forming a first gate insulating layer in the low voltage region;

forming a second gate insulating layer in the high voltage region;

forming a first conductive layer on the first gate insulating layer and the second gate insulating layer;

forming a triple layer on the first conductive layer and on the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer;

forming a second conductive layer over the triple layer;

forming a trench type device isolation layer in the substrate to isolate the low voltage region, the high voltage region, and the cell array region from each other;

forming a high conductivity layer over the substrate;

patterning the high conductivity layer, the second conductive layer, the triple layer, the second gate insulating layer, and the first gate insulating layer to form a second gate pattern in the high voltage region and a first gate pattern in the low voltage region;

patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region;

removing portions of the high conductivity layer, the second conductive layer, and the triple layer from the second gate pattern and the first gate pattern to form a butting region that exposes the first conductive layer;

forming an interlayer insulating layer over the substrate;

patterning the interlayer insulating layer to form contact holes that expose portions of the butting regions; and

filling the contact holes with contact plugs.

11. The method of claim 10, further comprising:

forming the first gate insulating layer and the first conductive layer in the cell array region; and

removing the first conductive layer in the cell array region, thereby exposing the substrate in the cell array region.

12. The method of claim 10, wherein the substrate further includes a resistor region, the method further comprising:

forming the second gate insulating layer, the first conductive layer, the triple layer, the second conductive layer, and the high-conductivity layer in the resistor region,

patterning the high-conductivitv layer, the second conductive layer, the triple layer, the first conductive layer, and the second gate insulating layer, thereby forming a resistor pattern in the resistor region;

removing the high-conductivity layer, the second conductive layer, and the triple layer from the resistor pattern;

forming an interlayer insulating layer over the resistor pattern; and

forming a contact hole in the interlayer insulating layer to extend over only the resistor pattern.

13. The method of claim 10, further comprising fonning insulating spacers on sidewalls of first gate pattern, the second gate pattern, and the cefl gate pattern.

14. The method of claim 10, wherein forming the high conductivity layer comprises sequentially stacking a conductive silicon layer and a conductive metal layer.

15. A method comprising:

forming a device isolation layer on a substrate to define a low voltage region, a high voltage region, and a cell array region;

forming a first gate insulating layer on the substrate in the low voltage region;

forming a second gate insulating layer on the substrate in the high voltage region;

forming a first conductive layer over the first gate insulating layer in the low voltage region and the second gate insulating layer in the high voltage region;

forming a triple layer on the substrate of the cell array region and on the first conductive layer, the triple layer including a tunneling insulation layer, a charge storage layer, and a blocking insulation layer;

forming a second conductive layer on the triple layer;

removing the second conductive layer and the triple layer from the low voltage region and the high voltage region;

forming a high conductivity layer on the first conductive layer in the low voltage region and in the high voltage region, and on the second conductive layer in the cell array region;

patterning the high conductivity layer, the first conductive layer, the first gate insulation layer, and the second gate insulation layer to form a first gate pattern in the low voltage region and a second gate pattern in the high voltage region; and

patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region.

16. The method of claim 15, flurther comprising:

forming the first gate insulating layer and the first conductive layer in the cell array region; and

removing the first conductive layer in the cell array region, thereby exposing the substrate in the cell array region.

17. The method of claim 15, further comprising:

forming an interlayer insulating layer over the cell gate pattern, the first gate pattern, and the second gate pattern;

patterning the interlayer insulating layer to form contact holes that expose a portion of the high conductivity layer in each of the cell gate pattern, the first gate pattern, and the second gate pattern; and

filling the contact holes with contact plugs.

18. The method of claim 15, wherein the substrate further includes a resistor region, the method further comprising:

forming the second gate insulating layer, the first conductive layer, the triple layer, the second conductive layer, and the high-conductivity layer in the resistor region;

patterning the high-conductivity layer, the second conductive layer, the triple layer, the first conductive layer, and the second gate insulating layer, thereby forming a resistor pattern in the resistor region;

removing the high conductivity layer, the second conductive layer, and the triple layer from the resistor pattern to expose the first conductive layer of the resistor pattern;

forming the interlayer insulating layer over the first conductive layer of the resistor pattern; and

forming a contact hole through the interlayer insulating layer that extends only over the resistor pattern.

19. A method comprising:

providing a substrate that includes a low voltage region, a high voltage region, and a cell array region;

forming a first gate insulating layer in the low voltage region;

forming a second gate insulating layer in the high voltage region;

forming a first conductive layer on the first gate insulating layer and second gate insulating layer;

forming a triple layer on the substrate of the cell array region and on the first conductive layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer;

forming a second conductive layer on the triple layer;

removing the second conductive layer and the triple layer from the low voltage region and the high voltage region;

forming a trench type device isolation layer to isolate the low voltage region, the high voltage region, and the cell array region from each other;

forming a high conductivity layer over the substrate;

patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region,

patterning the high conductivity layer, the first conductive layer, the first gate insulating layer, and the second insulating layer to form a first gate pattern in the low voltage region, and to form a second gate pattern in the high voltage region;

forming an interlayer insulating layer over the substrate;

patterning the interlayer insulating layer to form contact holes that expose a portion of the high conductivity layer of each of the cell gate pattern, the first gate pattern, and the second gate pattern; and

filling the contact holes with contact plugs.

20. The method of claim 19, further comprising:

forming the first gate insulating layer and the first conductive layer in the cell array region; and

removing the first conductive layer in the cell array region, thereby exposing the substrate in the cell array region.

21. The method of claim 19, wherein the substrate further includes a resistor region, the method further comprising:

forming the second gate insulating layer in the resistor region;

forming the second gate insulating layer, the first conductive layer, the triple layer, the second conductive layer, and the high-conductivity layer in the resistor region;

patterning the high-conductivitv layer, the second conductive layer, the triple layer, the first conductive layer and the second sate insulating layer, thereby forming a resistor pattern in the resistor region;

removing the high conductivity layer, the second conductive layer, and the triple layer from the resistor pattern to expose the first conductive layer of the resistor pattern;

forming the interlayer insulating layer over the first conductive layer of the resistor pattern; and

forming a contact hole that exposes only the resistor pattern.

22. The method of claim 19, further comprising forming insulating spacers on sidewalls of the cell gate pattern, the first gale pattern, and the second gate pattern.

23. The method of claim 19, wherein forming the high conductivity layer comprises sequentially stacking a conductive silicon layer and a conductive metal layer.