Method of forming a non-volatile memory device having floating trap type memory cell
First Claim
1. A method comprising:
- forming a device isolation layer in a substrate to define a low voltage region, a high voltage region, and a cell array region therein;
forming a first gate insulating layer on the substrate in the low voltage region;
forming a second gate insulating layer on the substrate in the high voltage region;
forming a first conductive layer overlying the low voltage region and the high voltage region;
forming a triple layer on the first conductive layer and on the substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer; and
forming a second conductive layer on the triple layer.
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Abstract
A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.
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Citations
23 Claims
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1. A method comprising:
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forming a device isolation layer in a substrate to define a low voltage region, a high voltage region, and a cell array region therein; forming a first gate insulating layer on the substrate in the low voltage region; forming a second gate insulating layer on the substrate in the high voltage region; forming a first conductive layer overlying the low voltage region and the high voltage region; forming a triple layer on the first conductive layer and on the substrate in the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer; and forming a second conductive layer on the triple layer. - View Dependent Claims (2, 3)
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4. A method comprising:
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forming a device isolation layer in a substrate to define a high voltage region, a low voltage region, and a cell array region therein; forming a first gate insulating layer on the substrate in the low voltage region; forming a second gate insulating layer on the substrate in the high voltage region; forming a first conductive layer on the first gate insulating layer and the second gate insulating layer; forming a triple layer on the first conductive layer and the substrate in the cell array region, the triple layer including a tunneling insulation layer, a charge storage layer, and a blocking insulation layer; forming a second conductive layer on the triple layer; patterning the second conductive layer, the triple layer, the first conductive layer, the first gate insulating layer, and the second gate insulating layer to form a second gate pattern in the high voltage region, a first gate pattern in the low voltage region; patterning the second conductive layer, the triple layer to form a cell gate pattern in the cell array region; removing portions of the second conductive layer and the triple layer from the second gate pattern and from the first gate pattern to form butting regions that expose portions of the first conductive layer; forming an interlayer insulating layer overlying the resulting structure; patterning the interlayer insulating layer to form contact holes that expose portions of the butting regions; and filling the contact holes with contact plugs. - View Dependent Claims (5, 6, 7, 8, 9)
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10. A method comprising:
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providing a substrate that includes a low voltage region, a high voltage region, and a cell array region; forming a first gate insulating layer in the low voltage region; forming a second gate insulating layer in the high voltage region; forming a first conductive layer on the first gate insulating layer and the second gate insulating layer; forming a triple layer on the first conductive layer and on the cell array region, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer; forming a second conductive layer over the triple layer; forming a trench type device isolation layer in the substrate to isolate the low voltage region, the high voltage region, and the cell array region from each other; forming a high conductivity layer over the substrate; patterning the high conductivity layer, the second conductive layer, the triple layer, the second gate insulating layer, and the first gate insulating layer to form a second gate pattern in the high voltage region and a first gate pattern in the low voltage region; patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region; removing portions of the high conductivity layer, the second conductive layer, and the triple layer from the second gate pattern and the first gate pattern to form a butting region that exposes the first conductive layer; forming an interlayer insulating layer over the substrate; patterning the interlayer insulating layer to form contact holes that expose portions of the butting regions; and filling the contact holes with contact plugs. - View Dependent Claims (11, 12, 13, 14)
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15. A method comprising:
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forming a device isolation layer on a substrate to define a low voltage region, a high voltage region, and a cell array region; forming a first gate insulating layer on the substrate in the low voltage region; forming a second gate insulating layer on the substrate in the high voltage region; forming a first conductive layer over the first gate insulating layer in the low voltage region and the second gate insulating layer in the high voltage region; forming a triple layer on the substrate of the cell array region and on the first conductive layer, the triple layer including a tunneling insulation layer, a charge storage layer, and a blocking insulation layer; forming a second conductive layer on the triple layer; removing the second conductive layer and the triple layer from the low voltage region and the high voltage region; forming a high conductivity layer on the first conductive layer in the low voltage region and in the high voltage region, and on the second conductive layer in the cell array region; patterning the high conductivity layer, the first conductive layer, the first gate insulation layer, and the second gate insulation layer to form a first gate pattern in the low voltage region and a second gate pattern in the high voltage region; and patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region. - View Dependent Claims (16, 17, 18)
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19. A method comprising:
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providing a substrate that includes a low voltage region, a high voltage region, and a cell array region; forming a first gate insulating layer in the low voltage region; forming a second gate insulating layer in the high voltage region; forming a first conductive layer on the first gate insulating layer and second gate insulating layer; forming a triple layer on the substrate of the cell array region and on the first conductive layer, the triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer; forming a second conductive layer on the triple layer; removing the second conductive layer and the triple layer from the low voltage region and the high voltage region; forming a trench type device isolation layer to isolate the low voltage region, the high voltage region, and the cell array region from each other; forming a high conductivity layer over the substrate; patterning the high conductivity layer, the second conductive layer, and the triple layer to form a cell gate pattern in the cell array region, patterning the high conductivity layer, the first conductive layer, the first gate insulating layer, and the second insulating layer to form a first gate pattern in the low voltage region, and to form a second gate pattern in the high voltage region; forming an interlayer insulating layer over the substrate; patterning the interlayer insulating layer to form contact holes that expose a portion of the high conductivity layer of each of the cell gate pattern, the first gate pattern, and the second gate pattern; and filling the contact holes with contact plugs. - View Dependent Claims (20, 21, 22, 23)
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Specification