DMOS device having a trenched bus structure

• US 7,084,457 B2
• Filed: 02/05/2004
• Issued: 08/01/2006
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chuang, Chiao-Shun, Hsieh, Hsin-Huang, Tseng, Mao-Song, Chang, Chien-Ping
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US10/774,212
• Publication Number:
  US 20040217416A1
• Time in Patent Office: 908 Days
• Field of Search: 257329-331, 257/333, 257/335, 257E29262-265, 257/E29.257, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/329
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Claims

1. A trenched DMOS device formed atop an N+ silicon substrate with an N epitaxial layer thereon including a device region and a bus region neighboring the device region, the device region comprising:

a P substrate, formed in the epitaxial layer and extending to a top surface thereof, a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof;

a gate oxide layer formed in the DMOS trenches and extending to cover the top surface of the P substrate;

a plurality of polysilicon gates formed in the DMOS trenches;

a plurality of N+ source regions formed in the P substrate adjacent the DMOS trenches;

a plurality of P+ diffused regions formed in the P substrate and each being interposed between two of the N+ source regions;

a first isolation layer formed over the P substrate to cover the polysilicon gate electrodes; and

a source metal contact layer formed on the first isolation layer and connecting to the N+ source regions and the P+ diffused regions;

and the bus region comprising;

a P substrate, formed in the epitaxial layer and extending to a top surface of the epitaxial layer, a field oxide layer being formed on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;

a gate oxide layer formed in the bus trench and extending to cover a top surface of the P substrate;

a polysilicon bus formed in the bus trench and having a top surface disposed at a lower level than the top surface of the field oxide layer;

a second isolation layer covering the field oxide layer and having an opening to expose the polysilicon bus; and

a metal line formed atop the polysilicon bus.

2. The trenched DMOS device of claim 1, wherein the P substrate of the device region and the P substrate of the bus region are formed by ion implantation simultaneously.

3. The trenched DMOS device of claim 1, wherein the gate oxide layer of the device region and the gate oxide layer of the bus region are formed simultaneously.

4. The trenched DMOS device of claim 1, wherein the polysilicon gate and the polysilicon bus are formed by depositing a polysilicon layer in the DMOS trenches and the bus trench and using the gate oxide layers as etch stop layers to etch the polysilicon layer.

5. The trenched DMOS device of claim 1, wherein the plurality of N+ source regions are formed in the P substrate on opposite sides of each of the DMOS trenches.

6. A semiconductor device set which comprises at least two types of devices, each of the two types of devices having a trench feature;

wherein the first device comprises a gate oxide formed in the trench feature, a polysilicon layer formed on the gate oxide in the trench features, a first isolation layer formed on the polysilicon layer and having an opening, and a metal layer formed on the first isolation layer and filling the opening of the first isolation layer; and

wherein the second device comprises a dielectric layer formed adjacent an opening at a top of the trench feature on opposite sides of the trench feature which extends downward from a top surface of the dielectric layer, a gate oxide formed in the trench feature and over the dielectric layer, a polysilicon layer formed on the gate oxide in the trench feature including a space below the top of the trench feature between the top surface of the dielectric layer and an upper surface of the polysilicon layer with the dielectric layer disposed on opposite sides thereof, a second isolation layer formed on the dielectric layer and having an opening to expose the polysilicon layer, and a metal layer formed on the polysilicon layer.

7. The semiconductor device set of claim 6, wherein the at least two types of devices are formed on a silicon substrate.

8. The semiconductor device set of claim 7, wherein the silicon substrate has an epitaxial layer formed thereon.

9. The semiconductor device set of claim 8, wherein the epitaxial layer has a P substrate thereon.

10. The semiconductor device set of claim 9, wherein each trench feature extends through the P substrate to an area below a top surface of the epitaxial layer.

11. The semiconductor device set of claim 9, wherein a plurality of N source regions and a plurality of P regions are formed in the P substrate.

12. The semiconductor device set of claim 11, wherein at least two of the N source regions formed in the P substrate are disposed adjacent to and on opposites sides of one of the first devices, and wherein at least one of the P regions formed in the P substrate is disposed between two adjacent N source regions.

13. The semiconductor device set of claim 8, wherein the epitaxial layer is an N epitaxial layer.

14. The semiconductor device set of claim 7, wherein the silicon substrate is an N substrate.

15. The semiconductor device set of claim 6 wherein the dielectric layer in the second device comprises a field oxide layer.