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DMOS device having a trenched bus structure

  • US 7,084,457 B2
  • Filed: 02/05/2004
  • Issued: 08/01/2006
  • Est. Priority Date: 04/29/2003
  • Status: Active Grant
First Claim
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1. A trenched DMOS device formed atop an N+ silicon substrate with an N epitaxial layer thereon including a device region and a bus region neighboring the device region, the device region comprising:

  • a P substrate, formed in the epitaxial layer and extending to a top surface thereof, a plurality of DMOS trenches extending downward through the P substrate from a top surface thereof;

    a gate oxide layer formed in the DMOS trenches and extending to cover the top surface of the P substrate;

    a plurality of polysilicon gates formed in the DMOS trenches;

    a plurality of N+ source regions formed in the P substrate adjacent the DMOS trenches;

    a plurality of P+ diffused regions formed in the P substrate and each being interposed between two of the N+ source regions;

    a first isolation layer formed over the P substrate to cover the polysilicon gate electrodes; and

    a source metal contact layer formed on the first isolation layer and connecting to the N+ source regions and the P+ diffused regions;

    and the bus region comprising;

    a P substrate, formed in the epitaxial layer and extending to a top surface of the epitaxial layer, a field oxide layer being formed on the P substrate and a bus trench extending down from a top surface of the field oxide layer to a lower portion of the P substrate;

    a gate oxide layer formed in the bus trench and extending to cover a top surface of the P substrate;

    a polysilicon bus formed in the bus trench and having a top surface disposed at a lower level than the top surface of the field oxide layer;

    a second isolation layer covering the field oxide layer and having an opening to expose the polysilicon bus; and

    a metal line formed atop the polysilicon bus.

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