Parallel bus debugging tool

• US 7,084,618 B2
• Filed: 12/08/2003
• Issued: 08/01/2006
• Est. Priority Date: 12/08/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Slutz, Mark, Schmitz, William, Voorhees, William
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US10/731,534
• Publication Number:
  US 20050134163A1
• Time in Patent Office: 967 Days
• Field of Search: None
• US Class Current: 324/754.03
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults

Abstract

A system and method for testing the signals on a parallel communication bus uses a single printed circuit board that connects to the bus. The signals from the bus may be passively and actively filtered prior to a multiplexer. The multiplexer may be controlled by a variety of inputs, including communications over a second bus by a remote device. The output of the multiplexer is one or more probe points that may be connected to a measurement device.

Claims

1. A switchable probe board for probing a parallel bus comprising:

a connector for connecting into said parallel bus;

a plurality of signal paths corresponding to individual signals of said parallel bus, each of said plurality of signal paths having a passive filter, and an adjustable filter circuit, said plurality of signal paths being electrically communicated to said connector;

a switch matrix connected to each of said plurality of signal paths and having at least one output; and

a controller adapted to configure said switch matrix to connect one of said plurality of signal paths to said at least one output, said controller having an input;

wherein said switchable probe board is a single printed circuit board.

2. The switchable probe board of claim 1 wherein said controller comprises dip switches.

3. The switchable probe board of claim 1 wherein said controller comprises a microprocessor programmable to cause said switch matrix to sequentially switch a predetermined set of said plurality of signal paths to said at least one output.

4. The switchable probe board of claim 3 wherein said controller communicates on a second communications bus.

5. The switchable probe board of claim 4 wherein said controller is programmed by a second device communicating over said second communications bus.

6. The switchable probe board of claim 1 wherein said adjustable filter circuit receives a training pattern of signals on said parallel bus and said adjustable filter circuit is set to a skew value based on said training pattern.

7. The switchable probe board of claim 1 wherein said parallel bus is a SCSI bus.

8. The switchable probe board of claim 1 wherein said parallel bus is a PCI bus.

9. The switchable probe board of claim 1 further comprising mounting hardware for simulating the mounting hardware of a disk drive.

10. A method for probing a plurality of signals on a parallel bus comprising:

providing a switchable probe board having a connector adapted to connect into said parallel bus, a plurality of signal paths corresponding to individual signals of said parallel bus, each of said plurality of signal paths having a passive filter, and an adjustable filter circuit, said plurality of signal paths being electrically communicated to said connector, a switch matrix connected to each of said plurality of signal paths and having at least one output, and a controller for configuring said switch matrix to connect one of said plurality of signal paths to said at least one output, said controller having an input, wherein said switchable probe board is a single printed circuit board;

connecting said connector to said parallel bus;

connecting a test device to said at least one output;

causing said switch matrix to select a first of said plurality of signals to be connected to said at least one output by sending an input to said controller;

measuring said first of said plurality of signals using said test device;

causing said switch matrix to select a second of said plurality of signals to be connected to said at least one output by sending an input to said controller; and

measuring said second of said plurality of signals using said test device.

11. The method of claim 10 wherein said controller comprises dip switches.

12. The method of claim 10 wherein said controller comprises a microprocessor programmable to cause said switch matrix to sequentially switch a predetermined set of said plurality of signal paths to said at least one output.

13. The method of claim 12 wherein said controller communicates on a second communications bus.

14. The method of claim 13 wherein said controller is programmed by a second device communicating over said second communications bus.

15. The method of claim 10 wherein said adjustable filter circuit receives a training pattern of signals on said parallel bus and sets said adjustable filter circuit to a skew value based on said training pattern.

16. The method of claim 10 wherein said parallel bus is a SCSI bus.

17. The method of claim 10 wherein said parallel bus is a PCI bus.

18. The method of claim 10 further comprising mounting hardware for simulating the mounting hardware of a disk drive.

19. A switchable probe board for probing a parallel bus comprising:

a first means for connecting to said parallel bus;

a plurality of second means for preparing said signals in a fixed filter and an adjustable filter circuit, each of said plurality of second means corresponding to individual signals of said parallel bus, said plurality of second means being electrically communicated to said first means;

a third means for probing a signal;

a fourth means for selectively connecting one of said plurality of second means to said third means; and

a fifth means for controlling said fourth means, said fifth means having an input;

wherein said switchable probe board is a single printed circuit board.

20. The switchable probe board of claim 19 wherein said input to said fifth means comprises dip switches.

21. The switchable probe board of claim 19 wherein said fifth means comprises a microprocessor programmable to cause said fourth means to sequentially switch a predetermined set of said plurality of second means to said third means.

22. The switchable probe board of claim 21 wherein said fifth means communicates on a second communications bus.

23. The switchable probe board of claim 22 wherein said fifth means is programmed by a second device communicating over said second communications bus.

24. The switchable probe board of claim 19 wherein said adjustable filter circuit receives a training pattern of signals on said parallel bus and sets said adjustable filter circuit to a skew value based on said training pattern.

25. The switchable probe board of claim 19 wherein said parallel bus is a SCSI bus.

26. The switchable probe board of claim 19 wherein said parallel bus is a PCI bus.

27. The switchable probe board of claim 19 further comprising a sixth means for mounting said switch probe board wherein said sixth means simulates the mounting hardware of a disk drive.