Semiconductor memory device and method of operating same

• US 7,085,156 B2
• Filed: 04/01/2005
• Issued: 08/01/2006
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon, S.A.
• Inventors: Ferrant, Richard, Okhonin, Serguei, Carman, Eric, Bron, Michel
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US11/096,970
• Publication Number:
  US 20050174873A1
• Time in Patent Office: 487 Days
• Field of Search: 365/174, 365/181, 257/905, 257/906, 257/E27.084, 257/E21.646
• US Class Current: 365/174
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Claims

1. An integrated circuit device comprising:

a semiconductor memory array, including;

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes a transistor having;

a source region;

a drain region;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and

a gate spaced apart from, and capacitively coupled to, the body region;

wherein each memory cell further includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell wherein the second charge is substantially provided by removing charge from the body region through the source region of the corresponding transistor; and

wherein the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells is connected to the same source line and wherein the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to the same word line; and

wherein one or more predetermined memory cells of the first row are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state.

2. The semiconductor memory array of claim 1 wherein:

each memory cell of the first row of semiconductor dynamic random access memory cells is programmed to the first data state by applying (1) a control signal, having a first amplitude, to the gate of the transistor of each memory cell of the first row and (2) a control signal, having a second amplitude, to the drain region of the transistor of each memory cell of the first row; and

the one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are programmed to the second data state by applying (1) a control signal, having a third amplitude, to the gate of the transistor of the one or more predetermined memory cells, (2) a control signal, having an fourth amplitude, to the drain region of the transistor of the one or more predetermined memory cells, and (3) a control signal, having a fifth amplitude, to the source region of the transistor of the one or more predetermined memory cells of the first row.

3. The device of claim 1 wherein the other memory cells of the first row of semiconductor dynamic random access memory cells are maintained in the first data state, while the one or more predetermined memory cells are programmed to the second data state by applying a control signal, having the third amplitude, to the gate of the transistor of the other memory cells and a control signal, having a sixth amplitude, to the drain region of the transistor of the other memory cells.

4. The device of claim 3 wherein the one or more predetermined memory cells are read by applying a control signal, having a seventh amplitude, to the gate of the transistor of each predetermined memory cell and a control signal, having an eight amplitude, to the drain region of the transistor of each predetermined memory cell.

5. The device of claim 4 wherein all of the memory cells of a second row of semiconductor dynamic random access memory cells are maintained in an inhibit state while the predetermined memory cells of the first row of semiconductor dynamic random access memory cells are read.

6. The device of claim 4 wherein all of the memory cells of a second row are maintained in an inhibit state while the one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are read by applying a control signal, having a ninth amplitude, to the gate of each transistor of the memory cells of the second row.

7. The device of claim 1 wherein the transistor of each memory cell of the first row of semiconductor dynamic random access memory cells shares a drain region with a transistor of an adjacent memory cell of a second row of semiconductor dynamic random access memory cells, wherein the first and second rows of memory cells are adjacent rows.

8. The device of claim 7 wherein the gate of the transistor of each memory cell of the second row of semiconductor dynamic random access memory cells is connected to a second word line.

9. The device of claim 8 wherein the source region of the transistor of each memory cell of the second row of semiconductor dynamic random access memory cells is connected to a second source line.

10. The device of claim 1 wherein:

the source region of the transistor of each memory cell corresponding to a second row of semiconductor dynamic random access memory cells is connected to a second source line and wherein the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line, wherein the first and second rows of semiconductor dynamic random access memory cells are adjacent rows; and

the source region of the transistor of each memory cell corresponding to a third row of semiconductor dynamic random access memory cells is connected to a third source line and wherein the gate of the transistor of each memory cell corresponding to the third row of semiconductor dynamic random access memory cells is connected to a third word line, wherein the first and third rows of semiconductor dynamic random access memory cells are adjacent rows.

11. The semiconductor memory array of claim 10 wherein all of the memory cells of the second and third rows are maintained in an inhibit state while the memory cells of the first row are read.

12. The semiconductor memory array of claim 10 wherein all of the memory cells of the second and third rows are maintained in an inhibit state while the memory cells of the first row are read by applying a control signal having a ninth amplitude to the gate of the transistor of each memory cell of the second and third rows.

13. An integrated circuit device, comprising:

a semiconductor memory array, including;

a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns, each semiconductor dynamic random access memory cell includes a transistor having;

a source region;

a drain region;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and

a gate spaced apart from, and capacitively coupled to, the body region;

wherein each memory cell further includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell wherein the second charge is substantially provided by removing charge from the body region through the source region of the corresponding transistor; and

wherein the source region of the transistor of each memory cell corresponding to a first row of semiconductor dynamic random access memory cells is connected to a first source line and wherein the gate of the transistor of each memory cell corresponding to the first row of semiconductor dynamic random access memory cells is connected to a first word line;

wherein the source region of the transistor of each memory cell corresponding to a second row of semiconductor dynamic random access memory cells is connected to a second source line and wherein the gate of the transistor of each memory cell corresponding to the second row of semiconductor dynamic random access memory cells is connected to a second word line; and

wherein the first and second rows of semiconductor dynamic random access memory cells are adjacent rows; and

wherein one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are programmed to the second data state by programming each memory cell of the first row to the first data state and thereafter programming the one or more predetermined memory cells of the first row to the second data state and wherein the memory cells of the second row of semiconductor dynamic random access memory cells are maintained in a fixed state while the one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are programmed to the second data state.

14. The semiconductor memory array of claim 13 wherein:

each memory cell of the first row of semiconductor dynamic random access memory cells is programmed to the first data state by applying (1) a control signal, having a first amplitude, to the gate of the transistor of each memory cell of the first row and (2) a control signal, having a second amplitude, to the drain region of the transistor of each memory cell of the first row; and

the one or more predetermined memory cells of the first row of semiconductor dynamic random access memory cells are programmed to the second data state by applying (1) a control signal, having a third amplitude, to the gate of the transistor of the one or more predetermined memory cells, (2) a control signal, having an fourth amplitude, to the drain region of the transistor of the one or more predetermined memory cells, and (3) a control signal, having a fifth amplitude, to the source region of the transistor of the one or more predetermined memory cells of the first row.

15. The device of claim 13 wherein the other memory cells of the first row are maintained in the first data state, while the one or more predetermined memory cells are programmed to the second data state by applying a control signal, having the third amplitude, to the gate of the transistor of the other memory cell and a control signal, having a sixth amplitude, to the drain region of the transistor of the other memory cells.

16. The semiconductor memory array of claim 13 wherein all of the memory cells of the first row of semiconductor dynamic random access memory cells are read by applying a control signal, having a seventh amplitude, to the gate of the transistor of each memory cell of the first row, and a control signal, having an eight amplitude, to the drain region of the transistor of each memory cell of the first row.

17. The semiconductor memory array of claim 16 wherein all of the memory cells of the second row are maintained in an inhibit state while the memory cells of the first row are read.

18. The semiconductor memory array of claim 16 wherein all of the memory cells of the second row are maintained in an inhibit state while the memory cells of the first row are read by applying a control signal having a ninth amplitude to the gate of the transistor of each memory cell of the second row.

19. The device of claim 13 wherein the source region of the transistor of each memory cell corresponding to a third row of semiconductor dynamic random access memory cells is connected to a third source line and wherein the gate of the transistor of each memory cell corresponding to the third row of semiconductor dynamic random access memory cells is connected to a third word line, wherein the first and third rows of semiconductor dynamic random access memory cells are adjacent rows.

20. The semiconductor memory array of claim 19 wherein all of the memory cells of the second and third rows are maintained in an inhibit state while the memory cells of the first row are read.

21. The semiconductor memory array of claim 13 wherein the transistors of the memory cells of the first and second rows share drain regions.