xDSL communications systems using shared/multi-function task blocks

• US 7,085,285 B2
• Filed: 03/01/2001
• Issued: 08/01/2006
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): Phan, Tri H.
• Application Number:
  US09/797,778
• Publication Number:
  US 20010047434A1
• Time in Patent Office: 1,979 Days
• Field of Search: 370485-495, 370/463, 375/220, 375/222
• US Class Current: 370/463
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A communications system including a shared signal circuit for performing a set of signal processing operations on both receive data and transmit data. The signal processing circuit is also shared by a plurality of communication ports. To further enhance operation of the system, the computing resources include a set of independent application specific (ASIC) logic circuits, with at least some of the ASICs selectively performing at least one of a first signal processing operation and a second signal processing operation on data in response to control information embedded in an input data object.

Claims

1. A communications system comprising:

a digital data buffer circuit for storing digital data, said digital data including both receive data and transmit data; and

a shared signal processing circuit for performing a set of signal processing operations on both said receive data and said transmit data, said set of signal processing operations associated with a digital subscriber loop (DSL) based communications transmission, said shared signal processing circuit having computing resources shared by a receive task and a transmit task;

said computing resources including a set of independent application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said set of independent ASIC logic circuits including at least one multi-tasking ASIC logic circuit, and which multi-tasking ASIC logic circuit, during a single period of said common clock, selectively performs at least one of a first signal processing operation on said receive data or a second signal processing operation on said transmit data; and

wherein said multi-tasking ASIC logic circuit performs either a transport convergence transmit related operation or a transport convergence receive related operation on a DMT based symbol associated with said digital data.

2. A communications system comprising:

a digital data buffer circuit for storing digital data, said digital data including both receive data and transmit data; and

a shared signal processing circuit for performing a set of signal processing operations on both said receive data and said transmit data, said set of signal processing operations associated with a digital subscriber loop (DSL) based communications transmission, said shared signal processing circuit having computing resources shared by a receive task and a transmit task;

said computing resources including a set of independent application specific (ASIC) logic circuits interconnected by a local bus and using a common clock, said set of independent ASIC logic circuits including at least one multi-tasking ASIC logic circuit, and which multi-tasking ASIC logic circuit, during a single period of said common clock, selectively performs at least one of a first signal processing operation on said receive data or a second signal processing operation on said transmit data; and

wherein said multi-tasking ASIC logic circuit performs either a physical medium transmit related operation or a physical medium receive related operation on a DMT based symbol associated with said digital data.

3. A digital subscriber loop (DSL) communications system for performing data transmissions for a plurality of independent communications ports, the DSL communications system comprising:

a digital data buffer circuit for storing discrete multi-tone (DMT) symbols, said DMT symbols including both receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports; and

a shared signal processing circuit for performing a set of signal processing operations on both said receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports, said set of signal processing operations including both transmission convergence operations and physical medium dependent operations supporting an xDSL protocol standard in the data transmissions; and

said shared signal processing circuit including a set of application specific (ASIC) logic circuits using a common clock, each ASIC logic circuit being configured to perform a single signal processing operation associated with a receive DMT symbol or a transmit DMT symbol during a single period of said common clock; and

said set of ASIC logic circuits further including at least one multi-tasking ASIC logic circuit, which multi-tasking ASIC logic circuit performs at least two signal processing operations, such that during a single period of said common clock said multi-tasking ASIC logic circuit is selectively controlled to perform either a first type of signal processing operation on a receive DMT symbol or a second type of signal processing operation on transmit DMT symbol;

wherein said first type of signal processing operation and second type of signal processing operation are performed for each communication port from the plurality of independent communications ports, such that during any single period of said common clock said set of ASIC logic circuits is simultaneously processing a plurality of DMT symbols for the plurality of independent communications ports.

4. A method of operating a communications system comprising the steps of:

buffering receive digital data to be processed in a data receive path;

buffering transmit digital data already processed in a data transmit path;

performing a first set of signal processing operations on both said receive digital data and said transmit digital data using an interconnected set of independent application specific (ASIC) logic circuits coupled to a common bus;

clocking said interconnected set of independent application specific (ASIC) logic circuits with a common clock; and

using at least a first ASIC logic circuit from said interconnected set of independent application specific (ASIC) logic circuits in a multi-tasking capacity such that during a single period of said common clock, said first ASIC logic circuit selectively performs at least one of a first signal processing operation for said data receive path or a second signal processing operation for said data transmit path;

wherein a second set of interconnected independent ASIC logic circuits are used to perform a second set of signal processing operations for said data receive path and said data transmit path, said second set of interconnected independent ASIC logic circuits including a second ASIC used in a multi-tasking capacity such that during a single period of said common clock, both said first ASIC logic circuit and said second ASIC logic circuit selectively perform at least one of a first signal processing operation for said data receive path or a second signal processing operation for said data transmit path; and

wherein a software based processor is used to perform a third set of signal processing operations associated with said data receive path and said data transmit path, wherein said software based processor also uses said common clock to perform at least one of a first signal processing operation for said data receive path or a second signal processing operation for said data transmit path.

5. A method of performing data transmissions for a plurality of independent communications ports in a digital subscriber loop (DSL) communications system the method comprising the steps of:

(a) storing discrete multi-tone (DMT) symbols, said DMT symbols including both receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports; and

(b) providing computing resources in the form of a set of application specific (ASIC) logic circuits including;

1) one or more single task application specific (ASIC) logic circuits using a common clock, each single task ASIC logic circuit being configured to perform a single signal processing operation associated with a receive DMT symbol or a transmit DMT symbol during a single period of said common clock; and

2) at least one multi-tasking ASIC logic circuit coupled to said set of ASIC logic circuits, which multi-tasking ASIC logic circuit performs at least two signal processing operations, such that during a single period of said common clock said multi-tasking ASIC logic circuit is selectively controlled to perform either a first type of signal processing operation on a receive DMT symbol or a second type of signal processing operation on transmit DMT symbol; and

(c) performing a set of signal processing operations on both said receive DMT symbols and transmit DMT symbols for each communication port from the plurality of independent communications ports using said set of ASIC logic circuits, said set of signal processing operations including both transmission convergence operations and physical medium dependent operations supporting an xDSL protocol standard in the data transmissions;

wherein said first type of signal processing operation and second type of signal processing operation are performed for each communication port from the plurality of independent communications ports, such that during any single period of said common clock said set of ASIC logic circuits is simultaneously processing a plurality of DMT symbols for the plurality of independent communications ports.

6. The method of claim 5, further including a step of using a general purpose programmable processor executing software instructions to perform signal processing operations on said receive DMT symbols and transmit DMT symbols.

7. The method of claim 5 wherein said set of ASIC logic circuits includes at least one multi-tasking ASIC logic circuit for performing transmission convergence operations and at least one separate multi-tasking ASIC logic circuit for performing physical medium dependent operations.

8. The method of claim 5 further wherein said performing a set of signal processing operations step comprises handling both asynchronous transfer mode (ATM) based communications and Voice over DSL (VoDSL) communications.

9. A method of operating a multi-port communications system using an xDSL signaling protocol, the method comprising the steps of:

(a) providing a processing pipeline for performing physical medium dependent operations and transport convergence operations for a number of communications port based on the xDSL signaling protocol; and

(b) using a first portion of said processing pipeline for performing a first set of signal processing operations for each communications port from said number of communications port, said first portion of said processing pipeline including a first set of one or more shared ASIC computing circuits, said first set of one or more shared ASIC computing circuits being used for a transmission operation and a receive operation for said number of communications ports; and

(c) using a second portion of said processing pipeline for performing a second set of signal processing operations for each communications port from said number of communications port, said second portion of said processing pipeline including a second set of one or more shared ASIC computing circuits, said second set of one or more shared ASIC computing circuits also being used for a transmission operation and a receive operation for said number of communications ports; and

(d) using a third portion of said processing pipeline for performing a third set of signal processing operations for each communications port from said number of communications port, said third portion of said processing pipeline including a general purpose programmable processor used for a transmission operation and a receive operation for said number of communications ports; and

wherein said first, second and third portions of said processing pipeline use a common pipeline clock.

10. The method of claim 9, wherein during any common pipeline clock period, said processing pipeline is operating on a plurality of separate discrete multi-tone (DMT) symbols for a plurality of separate communications ports.

11. The method of claim 9, wherein said common pipeline clock is used as an interrupt by said general purpose programmable processor to initiate a transmission and/or a receive operation.

12. The method of claim 9, further including a step of providing a common data structure for exchanging input data and output results between said first, second and third portions of said processing pipeline.