Method and apparatus for reducing DC offsets in a communication system
First Claim
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1. A feedback loop circuit apparatus for reducing DC offset in a communication channel, comprising:
- a summer coupled to a receiver channel, wherein a receiver channel signal is coupled as an first input to said summer; and
an integrator comprising an input coupled to said receiver channel, wherein an output of said integrator is coupled as a second input to said summer, wherein said integrator includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration;
wherein said integrator has a time constant that is variable according to at least one control signal to vary a frequency response of the integrator.
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Abstract
Methods and apparatuses for reducing DC offsets in a communication system are described. In a first aspect, a feedback loop circuit reduces DC offset in a wireless local area network (WLAN) receiver channel. The frequency response of the feedback loop circuit can be variable. In a second aspect, a circuit provides gain control in a WLAN receiver channel. First and second automatic gain control (AGC) amplifiers are coupled in respective portions of the receiver channel. Circuits for monitoring DC offset, and for providing control signals for controlling the frequency response of the DC offset reducing circuits are also provided.
674 Citations
61 Claims
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1. A feedback loop circuit apparatus for reducing DC offset in a communication channel, comprising:
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a summer coupled to a receiver channel, wherein a receiver channel signal is coupled as an first input to said summer; and an integrator comprising an input coupled to said receiver channel, wherein an output of said integrator is coupled as a second input to said summer, wherein said integrator includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; wherein said integrator has a time constant that is variable according to at least one control signal to vary a frequency response of the integrator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for reducing DC offset in a communication channel, comprising the steps of:
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(1) integrating an output signal available at a first node to generate an integrated signal using an integrator circuit, wherein the integrator circuit includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; (2) summing the integrated signal with a receiver channel signal at a second node, wherein the first node is downstream from the second node in a receiver channel; and (3) varying a time constant associated with step (1) in response to at least one control signal to vary a frequency response of said integration. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30)
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29. A method for reducing DC offset in a communication channel, comprising the steps of:
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(1) measuring a DC offset voltage present in an output signal at a first node, including the step of integrating the output signal available at the first node to generate an integrated signal that includes the DC offset voltage, wherein said integrating is performed by an integrator circuit that includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; (2) removing the measured DC offset voltage from a receiver channel signal at a second node, wherein the first node is downstream from the second node in a receiver channel; and (3) varying a time constant of the integrator circuit in response to at least one control signal to vary a frequency response of the integrator circuit. - View Dependent Claims (31)
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32. A feedback loop circuit apparatus for reducing DC offset in a communication channel, comprising:
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a summer coupled to a receiver channel, wherein a receiver channel signal is coupled as an first input to said summer; and an integrator comprising an input coupled to said receiver channel, wherein an output of said integrator is coupled as a second input to said summer; wherein said integrator includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; wherein said variable resistor is varied to alter a frequency response of said integrator; wherein said variable resistor includes; a first resistor, a second resistor coupled in series with said first resistor, a first switch coupled in parallel to said second resistor, a third resistor coupled in series with said second resistor, and a second switch coupled in parallel to said third resistor. - View Dependent Claims (33, 34, 35, 36, 37)
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38. A method for reducing DC offset in a communication channel, comprising the steps of:
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(1) arranging an amplifier, capacitor, and variable resistor in an integrating amplifier configuration, wherein the variable resistor includes a first resistor, a first switch, a second resistor, a second switch, and a third resistor; (2) configuring the variable resistor, including the steps of; coupling the first switch in parallel across the second resistor, coupling the second resistor in series with the first resistor, coupling the second switch in parallel across the third resistor, and coupling the third resistor in series with the second resistor; (3) integrating an output signal available at a first node to generate an integrated signal, wherein said integrating is performed by an integrator circuit, wherein the integrator circuit includes the amplifier, capacitor, and variable resistor; (4) summing the integrated signal with a receiver channel signal at a second node, wherein the first node is downstream from the second node in a receiver channel; and (5) varying the frequency response of the integrator circuit in response to a control signal, including the step of varying the value of the variable resistor to alter the frequency response of the integrator circuit. - View Dependent Claims (39, 40, 41)
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42. A communications system that includes a feedback loop circuit for reducing DC offset in a communication channel, comprising:
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a summer coupled to a receiver channel, wherein a receiver channel signal is coupled as an first input to said summer; and an integrator comprising an input coupled to said receiver channel, wherein an output of said integrator is coupled as a second input to said summer, wherein said integrator includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; wherein said integrator has a time constant that is variable according to at least one control signal to vary a frequency response of the integrator. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. A communications system that includes a feedback loop circuit for reducing DC offset in a communication channel, comprising:
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a summer coupled to a receiver channel, wherein a receiver channel signal is coupled as an first input to said summer; and an integrator comprising an output coupled to said receiver channel, wherein an output of said integrator is coupled as a second input to said summer; wherein said integrator has a time constant that is variable according to at least one control signal to vary a frequency response of the integrator; wherein said integrator includes an amplifier, a capacitor, and a variable resistor arranged in an integrating amplifier configuration; wherein said variable resistor is varied to alter the frequency response of said integrator; wherein said variable resistor includes; a first resistor, a second resistor coupled in series with said first resistor; a first switch coupled in parallel across said second resistor; a third resistor coupled in series with said second resistor; and a second switch coupled in parallel across said third sensor. - View Dependent Claims (59, 60, 61)
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Specification