High sensitivity, high resolution detection of signals

• US 7,085,502 B2
• Filed: 03/14/2005
• Issued: 08/01/2006
• Est. Priority Date: 07/30/2002
• Status: Expired due to Fees

• Current Assignee: Amplification Technologies, Inc. (Powersafe Technology Corp.)
• Original Assignee: Amplification Technologies, Inc. (Powersafe Technology Corp.)
• Inventors: Shushakov, Dmitry A., Shubin, Vitaly E.
• Primary Examiner(s): Leung, Christina Y.
• Application Number:
  US11/080,019
• Publication Number:
  US 20050185266A1
• Time in Patent Office: 505 Days
• Field of Search: 398/202, 398/210, 250/265, 257/E31.075
• US Class Current: 398/202
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/70 Charge amplifiers

Abstract

A system and method providing for the detection of an input signal by distributing the input signal into independent signal components that are independently amplified. Detection of an input signal comprises generating from the input signal a plurality of spatially separate elementary charge components, each having a respective known number of elementary charges, the number of the plurality of spatially separate elementary charge components being a known monotonic function of the magnitude of said input signal; and independently amplifying each of the plurality of spatially divided elementary charge components to provide a respective plurality of signal charge packets, each signal charge packet having a second number of elementary charges greater than the respective known number by a respective amplification factor.

Claims

1. A semiconductor amplifier device that provides a signal representing the magnitude of an input signal, comprising:

a semiconductor region including a plurality of spatially separate charge amplifiers configured such that in response to said input signal being coupled into the semiconductor amplifier device (i) the number of said charge amplifiers excited is a known monotonic function of the input signal magnitude over a predetermined dynamic range of the input signal, and (ii) to within a statistically significant metric each excited charge amplifier is excited by a respective quantity of charge that is known in advance of sensing the input signal and is independent of the input signal magnitude; and

at least one readout electrode coupled to said charge amplifiers to provide an output signal representing the number of charge amplifiers excited by the input signal.

2. The semiconductor amplifier device according to claim 1, wherein the input signal is an optical signal coupled into the semiconductor amplifier device by optical absorption and photogeneration of electrical charge in the semiconductor region.

3. The semiconductor amplifier device according to claim 2, wherein the semiconductor region includes at least one first semiconductor layer for the optical absorption and photogeneration of electrical charge, and at least one other semiconductor layer containing the charge amplifiers.

4. The semiconductor amplifier device according to claim 1, wherein the input signal coupled into the semiconductor amplifier device is an electrical signal.

5. The semiconductor amplifier device according to claim 1, wherein the total number of said charge amplifiers is selected to provide for excited charge amplifiers to be excited, to within a statistically significant metric, by said respective quantity of charge over the predetermined dynamic range of the input signal.

6. The semiconductor amplifier device according to claim 1, wherein the respective quantity of charge that excites each charge amplifier is the same quantity to within a statistically significant metric.

7. The semiconductor amplifier device according to claim 1, wherein the respective quantity of charge that excites each charge amplifier is one electron to within a statistically significant metric.

8. The semiconductor amplifier device according to claim 1, wherein each charge amplifier employs avalanche multiplication.

9. The semiconductor amplifier device according to claim 8, wherein each charge amplifier comprises a plurality of avalanche multiplication regions configured such that in operation (i) the electric field intensity in each of the avalanche multiplication regions is sufficient for avalanche multiplication, and (ii) the electric field intensity between avalanche multiplication regions is insufficient for avalanche multiplication, such that in each excited charge amplifier the respective quantity of charge excites a first one of the avalanche multiplication regions to provide an initial charge packet by avalanche multiplication, and said initial charge packet drifts to, and is subject to avalanche multiplication within, a second one of said plurality of avalanche multiplication regions, each charge amplifier thereby providing for multi-stage avalanche multiplication.

10. The semiconductor amplifier device according to claim 8, wherein the semiconductor amplifier device is biased at a voltage that exceeds the breakdown voltage for avalanche multiplication by the charge amplifiers.

11. The semiconductor amplifier device according to claim 10, wherein the voltage exceeds the breakdown voltage by at least about five volts.

12. The semiconductor amplifier device according to claim 10, wherein each of the excited charge amplifiers generates a respective signal charge packet by avalanche multiplication of the respective quantity of charge by an amplification amount sufficient to detect each said respective signal charge packet.

13. The semiconductor amplifier device according to claim 1, wherein each of the excited charge amplifiers generates a respective signal charge packet by avalanche multiplication of the respective quantity of charge by an amplification amount sufficient to detect each said respective signal charge packet.

14. The semiconductor amplifier device according to claim 1, wherein each of the excited charge amplifiers outputs a respective signal charge packet, and the at least one readout electrode is coupled to the respective charge packets.

15. The semiconductor amplifier device according to claim 14, wherein said at least one readout element is coupled to sum the respective signal charge packets.

16. The semiconductor amplifier device according to claim 14, wherein the at least one readout electrode is implemented as a single readout electrode that contacts each of the plurality of conductive plugs, and that capacitively couples to each of the plurality of conductive integrating electrodes.

17. The semiconductor amplifier device according to claim 16, wherein said semiconductor is silicon and said first conductivity is p-type.

18. The semiconductor amplifier device according to claim 17, wherein said contact plug material is silicon carbide.

19. The semiconductor amplifier device according to claim 14, wherein the readout electrode is coupled to readout each of said plurality of signal charge packets individually.

20. The semiconductor amplifier device according to claim 14, wherein each of said plurality of signal charge packets is provided by a dosed charge accumulation mechanism that results in each of said plurality of signal charge packets having a given quantity of charge.

21. The semiconductor amplifier device according to claim 14, further comprising a plurality of independent integrators each respectively coupled to (i) at least one respective charge amplifier to accumulate the signal charge packets, and (ii) the readout element.

22. The semiconductor amplifier device according to claim 21, further comprising a plurality of quantifier elements, each quantifier element coupled to a respective charge amplifier to gate the operation of the charge amplifier in response to a predetermined quantity of charge accumulated by the integrator.

23. The semiconductor amplifier device according to claim 22, further comprising a plurality of governor elements, each governor element coupled to a respective integrator and operative in eliminating the charge accumulated by said integrator.

24. The semiconductor amplifier device according to claim 23, wherein each of the governors is operative in eliminating the charge accumulated by the respective integrator at time delay after the respective charge amplifier is excited.

25. The semiconductor amplifier device according to claim 24, wherein each of the governors is operative in eliminating the charge accumulated by the respective integrator at time delay after the respective charge amplifier switches from an amplifying state in which the respective charge amplifier generates the charge accumulated by the respective integrator to an off state in which the respective charge amplifier does not amplify charge.

26. The semiconductor amplifier device according to claim 25, wherein in the amplifying state each charge amplifier employs avalanche multiplication at a field that exceeds the breakdown field for avalanche multiplication, and wherein each of the governors is operative in eliminating the charge accumulated by the respective integrator at time delay after the time instant when the electric field in the charge amplifier decreases below the breakdown field for avalanche multiplication.

27. The semiconductor amplifier device according to claim 23, wherein each of the governors is operative in eliminating the charge accumulated by the respective integrator after the respective integrator accumulates the respective signal charge packet.

28. The semiconductor amplifier device according to claim 23, wherein each of the governors is implemented as a heterojunction.

29. The semiconductor amplifier device according to claim 22, wherein the predetermined quantity of charge accumulated by the integrator is predetermined as an amount sufficient for detection.

30. The semiconductor amplifier device according to claim 22, wherein said quantifier provides charge quenching of the amplification process in the charge amplifier upon the predetermined quantity of charge being accumulated by the integrator, such that the gain of the charge amplifier is independent of the statistics of the amplification mechanism.

31. The semiconductor amplifier device according to claim 21, wherein each of said integrators has a capacitance that includes the capacitance of said readout element.

32. The semiconductor amplifier device according to claim 1, wherein the semiconductor amplifier device is a monolithic semiconductor structure comprising:

a region of first conductivity and a plurality of spatially separate regions of opposite conductivity forming separate p-n junctions with the region of first conductivity;

a first conductive electrode conductively coupled to the region of first conductivity to provide a terminal that is common to each of the p-n junctions;

a plurality of conductive integrating electrodes, each conductive integrating electrode conductively coupled to at least a respective one of the spatially separate regions of opposite conductivity;

an insulating layer between the plurality of conductive integrating electrodes and the at least one readout electrode; and

a plurality of conductive plugs, each conductive plug contacting the at least one readout electrode and a respective one of said conductive integrating electrodes, the conductive plugs being made of a material that provides a first energy barrier for a carrier of said opposite conductivity to transport into the conductive plug from the spatially separate regions, and forms a second energy barrier for a carrier of said first conductivity type opposite to transport into the conductive plug from said at least one readout electrode.

33. The semiconductor amplifier device according to claim 32, wherein the charge that excites each excited charge amplifier is amplified by avalanche multiplication in local semiconductor regions of the first conductivity near the p-n junctions.

34. The semiconductor amplifier device according to claim 33, wherein the charge that excites each excited charge amplifier is amplified according to a self-limited gain mechanism.

35. The semiconductor amplifier device according to claim 34, wherein the semiconductor amplifier device is biased at a voltage that exceeds the breakdown voltage for avalanche multiplication by the charge amplifiers.

36. The semiconductor amplifier device according to claim 35, wherein each of the excited charge amplifiers generates a respective signal charge packet by avalanche multiplication of the respective quantity of charge by an amplification amount sufficient to detect each said respective signal charge packet.

37. The semiconductor amplifier device according to claim 1, wherein the semiconductor amplifier device is formed on a substantially planar semiconductor substrate, and each of the charge amplifiers provides for avalanche multiplication of charge carriers transported in a direction substantially normal to the substantially planar surface of the semiconductor substrate.

38. The semiconductor amplifier device according to claim 1, wherein the semiconductor amplifier device is formed on a substantially planar semiconductor substrate, and each of the charge amplifiers provides for avalanche multiplication of charge carriers transported in a lateral direction that is substantially parallel to the substantially planar surface of the semiconductor substrate.

39. The semiconductor amplifier device according to claim 1, wherein the input signal is provided as the output of a particle or x-ray sensor, thereby providing for improved detection in counter-terrorism applications.