Method and system for modeling and automatically generating an embedded system from a system-level environment

• US 7,085,702 B1
• Filed: 06/25/2002
• Issued: 08/01/2006
• Est. Priority Date: 10/16/2001
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Stroomer, Jeffrey D., Hwang, L. James
• Primary Examiner(s): Shah, Kamini
• Assistant Examiner(s): Lo, Suzanne
• Application Number:
  US10/180,857
• Time in Patent Office: 1,498 Days
• Field of Search: 703/15, 703/13
• US Class Current: 703/15
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

Method and system for modeling and automatically generating an embedded system from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. A processor design object is provided which defines a processor. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level and processor design objects. The system simulates behavior of the system-level design consistent with the processor, system-level functions, and behavior of a hardware definition from the hardware-level design objects that implement the user-selected ones of the system-level design objects.

Claims

1. A computer-implemented method for creating an electronic circuit design, comprising:

providing a plurality of user-selectable system-level design objects, wherein each system-level design object is defined by a system-level function, is parameterizable, and has at least one input data port, at least one output data port, and a clock-enable port, and each input and output data port has an associated, user-specified sample rate;

providing a plurality of hardware-level design objects, each hardware-level design object configured to generate a hardware definition of a hardware-level function, wherein one or more hardware-level design objects are combinable to implement each system-level design object;

providing a user-selectable processor design object that defines a processor;

instantiating a system-level design in a system-level design file in response to user control signals, the system-level design including user-selected ones of the system-level design objects and the processor design object;

simulating behavior of the system-level design consistent with the processor, the system-level functions and behavior of a hardware definition from the hardware-level design objects that implement the user-selected ones of the system-level design objects; and

in response to a signal to generate a hardware-level design from the system-level design file, generating a clock control hardware definition that includes an output port with a clock rate for each different sample rate, wherein each clock control output port is coupled to the clock-enable port of each system-level design object having an input data port with a sample rate equal to the clock rate of the clock control output port; and

generating hardware definitions for the hardware-level design objects that implement each user-selected system-level design object.

2. The method of claim 1, further comprising generating a hardware implementation from the system-level design that includes the processor design object and system-level design objects, which are implemented with the hardware-level design objects.

3. The method of claim 2, further comprising:

in response to a signal to generate a hardware-level design from the system-level design file,

supplementing the system-level design objects with clock-clear and clock-enable ports.

4. The method of claim 3, further comprising:

simulating behavior of the system-level design with user-specified input-data generators that generate system-level input data;

capturing the system-level input data generated by the input-data generators; and

generating a hardware definition for a first testbench component that provides the system-level input data as input data to the hardware definitions.

5. The method of claim 4, further comprising simulating behavior of the design defined by the processor design object, hardware definitions, and the testbench component.

6. The method of claim 5, further comprising:

capturing system-level output data generated during simulation of the system-level design;

generating a hardware definition for a second testbench component that compares output data generated during simulation of the design defined by the hardware definitions to output data captured during simulation of the system-level design.

7. The method of claim 2, further comprising:

simulating behavior of the design defined in the system-level design file with user-specified input-data generators that generate system-level input data;

capturing the system-level input data generated by the input-data generators; and

generating a hardware definition for a first testbench component that provides the system-level input data as input data to the hardware definitions.

8. The method of claim 7, further comprising simulating behavior of the design defined by the hardware definitions and the testbench component.

9. The method of claim 8, further comprising:

capturing system-level output data generated during simulation of the design defined in the system-level design file;

generating a hardware definition for a second testbench component that compares output data generated during simulation of the design defined by the hardware definitions to output data captured during simulation of the design defined in the system-level design file.

10. An apparatus for creating an electronic circuit design, comprising:

means for providing a plurality of user-selectable system-level design objects, wherein each system-level design object is defined by a system-level function, is parameterizable, and has at least one input data port, at least one output data port, and a clock-enable port, and each input and output data port has an associated, user-specified sample rate;

means for providing a plurality of hardware-level design objects, each hardware-level design object configured to generate a hardware definition of a hardware-level function, wherein one or more hardware-level design objects are combinable to implement each system-level design object;

means for providing a user-selectable processor design object that defines a processor;

means for instantiating a system-level design in a system-level design file in response to user control signals, the system-level design including user-selected ones of the system-level design objects and the processor design object;

means for simulating behavior of the system-level design consistent with the processor, the system-level functions and behavior of a hardware definition from the hardware-level design objects that implement the user-selected ones of the system-level design objects; and

means, responsive to a signal to generate a hardware-level design from the system-level design file, for generating a clock control hardware definition that includes an output port with a clock rate for each different sample rate, wherein each clock control output port is coupled to the clock-enable port of each system-level design object having an input data port with a sample rate equal to the clock rate of the clock control output port, and for generating hardware definitions for the hardware-level design objects that implement each user-selected system-level design object.

11. The apparatus of claim 10, further comprising means for generating a hardware implementation from the system-level design that includes the processor design object and system-level design objects, which are implemented with the hardware-level design objects.

12. The apparatus of claim 11, further comprising

means for supplementing the system-level design objects with clock-enable and clock-clear ports responsive to the signal to generate a hardware-level design from the system-level design file.

13. A system for creating an electronic circuit design, comprising:

a plurality of user-selectable system-level design objects, wherein each system-level design object is defined by a system-level function, is parameterizable, and has at least one input data port, at least one output data port, and a clock-enable port, and each input and output data port has an associated, user-specified sample rate;

at least one user-selectable processor design object that defines a processor;

a plurality of hardware-level design objects, each hardware-level design object configured to generate a hardware definition of a hardware-level function, wherein one or more hardware-level design objects are combinable to implement each system-level design;

a system-level simulation environment configured to instantiate a system-level design in a system-level design file, the system-level design including user-selected ones of the processor design object, system-level design objects, and simulate behavior of the system-level design consistent with the processor, system-level functions, and behavior of a hardware definition from the hardware-level design objects that implement the user-selected ones of the system-level design objects; and

a translator coupled to the system-level simulation environment, the translator configured to, in response to a signal to generate a hardware-level design from the system-level design file, generate a clock control hardware definition that includes an output port with a clock rate for each different sample rate, wherein each clock control output port is coupled to the clock-enable port of each system-level design object having an input data port with a sample rate equal to the clock rate of the clock control output port, and the translator further configured to generate hardware definitions for the hardware-level design objects that implement each user-selected system-level design object.

14. The system of claim 13, is further configured to, responsive to the signal to generate a hardware-level design from the system-level design file,

supplement the system-level design objects with clock-enable and clock-clear ports.

15. The system of claim 14, wherein the system-level simulation environment is configured to:

simulate behavior of the system-level design with user-specified input-data generators that generate system-level input data;

capture the system-level input data generated by the input-data generators; and

generate a hardware definition for a first testbench component that provides the system-level input data as input data to the hardware definitions.

16. The system of claim 15, wherein the system-level simulation environment is configured to:

capture system-level output data generated during simulation of the system-level design; and

generate a hardware definition for a second testbench component that compares output data generated during simulation of the design defined by the hardware definitions to output data captured during simulation of the system-level design.