Data transfer control device and electronic equipment

• US 7,085,855 B1
• Filed: 10/12/2000
• Issued: 08/01/2006
• Est. Priority Date: 10/15/1999
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Sato, Daisuke, Horiuchi, Hiroshi
• Primary Examiner(s): Vu, Thong
• Assistant Examiner(s): Nguyen, Hai V.
• Application Number:
  US09/686,914
• Time in Patent Office: 2,119 Days
• Field of Search: 709/253, 709/213, 709/224, 709/250, 710/107, 710/58, 710/129, 710/315, 710/33, 710/605, 710/316, 710/52, 386/46, 386/67, 702/122, 370/84, 370/463, 370/391, 370/389, 714/712
• US Class Current: 709/253
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0012 High speed serial bus, e.g. IEEE P1394
• CPC Class Codes: H04L 12/40078 Bus configuration home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 12/6418 Hybrid transport

Abstract

The objective of the present invention is to provide a data transfer control device and electronic equipment that guarantee stable operation even if a reset that clears the node topology information occurs. When a CPU (firmware) of a data transfer control device in accordance with the IEEE 1394 standard issues a data transfer start (or resume) command during a bus reset period, the execution of that command is canceled. The fact that the command has been canceled is informed to the CPU by an interrupt. The command is canceled by using a signal that is active during the bus reset period to mask a signal that goes active when a command is issued. When a pause command is issued, the transfer processing pauses at a previously determined pause location. Transfer data is automatically divided into a series of packets to be transferred continuously by the hardware. When a resume command and a pause command for transfer data have been issued together, the CPU executes the transfer processing in steps then pauses the transfer processing.

Claims

1. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising:

a control circuit which starts transfer processing when a processing unit issues a start command for data transfer, and resumes transfer processing when the processing unit issues a resume command for data transfer;

a transfer execution circuit which executes processing for dividing transfer data into a series of packets and transferring the divided series of packets continuously, when the processing unit issues the start command for data transfer;

a cancellation circuit which cancels an execution of one of the start command and the resume command, when the processing unit issues one of the start command and the resume command, respectively, during a period of a reset that clears node topology information; and

a circuit which informs the processing unit that command execution has been canceled by the reset,

wherein the cancellation circuit receives a reset period signal which becomes active during the period of the reset and makes a command signal corresponding to one of the issued start command and the issued resume command not to be transferred to the control circuit when the reset period signal becomes active, and

wherein the control circuit performs one of transfer starting and transfer resuming when the processing unit issues one of the start command and the resume command during a period other than the period of the reset.

2. The data transfer control device as defined in claim 1, further comprising:

an interrupt controller which issues an interrupt with respect to the processing unit when an execution of the start command or the resume command for data transfer is cancelled by the occurrence of the reset; and

factor storage register which informs the processing unit of a factor of the interrupt.

3. The data transfer control device as defined in claim 1,

wherein the cancellation circuit cancels the start command or the resume command by using a signal that goes active during the reset period to mask a signal that goes active when the processing unit issues the start command or the resume command.

4. The data transfer control device as defined in claim 1, further comprising:

a pause control circuit which pauses transfer processing at a previously determined location when the processing unit issues a data transfer pause command or when a transfer error occurs.

5. The data transfer control device as defined in claim 1,

wherein the reset is a bus reset as defined by the IEEE 1394 standard.

6. Electronic equipment comprising:

the data transfer control device as defined in claim 5;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

7. Electronic equipment comprising:

the data transfer control device as defined in claim 5;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

8. Electronic equipment comprising:

the data transfer control device as defined in claim 1;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

9. Electronic equipment comprising:

the data transfer control device as defined in claim 1;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

12. The data transfer control device as defined in claim 1,

wherein data transfer is performed in accordance with the IEEE 1394 standard.

13. Electronic equipment comprising:

the data transfer control device as defined in claim 12;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

14. Electronic equipment comprising:

the data transfer control device as defined in claim 12;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

10. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising:

a transfer execution circuit which executes processing for dividing transfer data into a series of packets and transferring the divided series of packets continuously, when processing unit issues a start command for data transfer; and

a pause control circuit which pauses a transfer processing after a step execution of the transfer processing, when the processing unit issues a resume command and a pause command for data transfer together,

wherein the pause control circuit pauses the transfer processing after the completion of the transfer processing of the step execution.

11. The data transfer control device as defined in claim 10,

wherein the pause control circuit executes the step execution and the pause of the transfer processing, based on a resume signal that goes active when the resume command is issued, and a delay pause signal that goes active after a delay of a given period after the resume signal goes active when the resume command and the pause command are issued together.

15. The data transfer control device as defined in claim 10,

wherein data transfer is performed in accordance with the IEEE 1394 standard.

16. Electronic equipment comprising:

the data transfer control device as defined in claim 15;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

17. Electronic equipment comprising:

the data transfer control device as defined in claim 15;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

18. Electronic equipment comprising:

the data transfer control device as defined in claim 10;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

19. Electronic equipment comprising:

the data transfer control device as defined in claim 10;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.