Managing a secure environment using a chipset in isolated execution mode
First Claim
1. An apparatus comprising:
- a PE handler storage to store a PE handler image to be loaded into an isolated memory area within a memory of a processing system after at least a portion of a chipset circuit of the processing system is initialized, the PE handler image to be executed by a processor of the processing system, the processor capable of operating in a normal execution mode and in an isolated execution mode; and
an initialization storage to configure the processing system in the isolated execution mode, the processor capable of accessing the isolated memory area when operating in the isolated execution mode.
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Accused Products
Abstract
A chipset is initialized in a secure environment for an isolated execution mode by an initialization storage. The secure environment has a plurality of executive entities and is associated with an isolated memory area accessible by at least one processor. The at least one processor has a plurality of threads and operates in one of a normal execution mode and the isolated execution mode. The executive entities include a processor executive (PE) handler. PE handler data corresponding to the PE handler are stored in a PE handler storage. The PE handler data include a PE handler image to be loaded into the isolated memory area after the chipset is initialized. The loaded PE handler image corresponds to the PE handler.
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Citations
53 Claims
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1. An apparatus comprising:
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a PE handler storage to store a PE handler image to be loaded into an isolated memory area within a memory of a processing system after at least a portion of a chipset circuit of the processing system is initialized, the PE handler image to be executed by a processor of the processing system, the processor capable of operating in a normal execution mode and in an isolated execution mode; and
an initialization storage to configure the processing system in the isolated execution mode, the processor capable of accessing the isolated memory area when operating in the isolated execution mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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storing a processor executive (PE) handler image in a PE handler storage of a chipset circuit, the chipset circuit in communication with a processor that supports a normal execution mode and an isolated execution mode, and in communication with a memory to include an isolated memory area accessible to the processor in the isolated execution mode; and
after at least a portion of the chipset circuit is initialized, loading the PE handler image into the isolated memory area. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A system comprising:
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a processor capable of selectively operating in a normal execution mode and, alternatively, in an isolated execution mode;
a memory to include an isolated memory area accessible to the processor in the isolated execution mode;
a chipset circuit in communication with the processor and the memory; and
a PE handler storage in the chipset circuit, the PE handler storage to store a PE handler image to be loaded into the isolated memory area after at least a portion of the chipset circuit is initialized. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. An apparatus comprising:
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a machine accessible medium; and
instructions encoded in the machine accessible medium, wherein the instructions, when executed by a processing system with a processor and a chipset circuit that supports a normal execution mode and an isolated execution mode, cause the processing system to perform operations comprising;
obtaining a processor executive (PE) handler image from a PE handler storage in the chipset circuit; and
after at least a portion of the chipset circuit is initialized, loading the PE handler image into an isolated memory area within a memory of the processing system, the isolated memory area accessible to the processor in the isolated execution mode. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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Specification