Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle state

• US 7,085,942 B2
• Filed: 05/21/2003
• Issued: 08/01/2006
• Est. Priority Date: 05/21/2003
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Kopley, Thomas E., Srikantam, Vamsi K.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Suryawanshi, Suresh
• Application Number:
  US10/443,555
• Publication Number:
  US 20040236971A1
• Time in Patent Office: 1,168 Days
• Field of Search: 713/300, 713/323, 713/320, 327/538, 327/544
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. In the method, independent determinations are performed. Each determination defines a respective set of the input states of the input state vector. Any conflict the definitions of any one or more of the input states is resolved in favor of the definition of the one or more of the input states that achieves the lowest idle power consumption when the input state vector incorporating the one or more of the input states in accordance with the definition is applied to the circuit inputs of the digital circuit in the idle state.

Claims

1. Apparatus for defining an input state vector for application to the circuit inputs of a digital circuit to achieve low power when said digital circuit is in an idle state, the apparatus comprising:

an input state set defining module operable to perform independent determinations defining respective sets of the input states of said input state vector; and

a conflict resolving module operable to resolve any conflict in the definitions of any one or more of said input states in favor of a definition of said one or more of said input states that achieves the lowest power consumption when said input state vector comprising said one or more of said input states in accordance with said definition is applied to the circuit inputs of said digital circuit in said idle state.

2. The apparatus of claim 1, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types; and

said input state vector defining module comprises;

an idle power value source having idle power values stored therein, said idle power values including idle power values for each one of said circuit element types, said idle power values for said one of said circuit element types corresponding to different states of the inputs of a circuit element of said one of said circuit element types, and

an idle power assessor coupled to said idle power value source, said idle power assessor operable during each determination to use said idle power values to determine, for each one of said circuit elements of a segment of said digital circuit subject to said determination, states of the inputs of said one of said circuit elements that would set said one of said circuit elements to a lowest-allowable idle power state when said digital circuit is in said idle state, said determining accounting for the logic constraints of said segment of said digital circuit, said states determined for ones of said inputs that constitute respective ones of said circuit inputs defining said respective set of said input states.

3. The apparatus of claim 1, in which:

said input state set defining module is operable to perform;

a first determination defining first ones of said input states, said first ones of said input states constituting a first set of the input states of said input state vector, and

a second determination, independent of said first determination, defining second ones of said input states, said second ones of said input states constituting a second set of the input states of said input state vector, said second determination and said first determination providing conflicting definitions of one of said input states; and

said conflict resolution module is operable to resolve said conflict in said definitions of said one of said input states in favor of the definition of said one of said input states that achieves the lower idle power consumption when said input state vector comprising said one of said input states in accordance with said definition is applied to said circuit inputs.

4. The apparatus of claim 1, in which said input state set defining module is additionally operable to divide said digital circuit into segments and to perform each of said determinations on a different one of said segments.

5. The apparatus of claim 1, in which said conflict resolving module is operable to resolve said any conflict in the definitions of at least two of said input states in favor of the combination of said at least two of said input states that achieves the lowest idle power consumption when said input state vector comprising said at least two of said input states in accordance with said combination is applied to said circuit inputs.

6. The apparatus of claim 1, in which said conflict resolving module is operable to resolve said any conflict in the definitions of said one or more of said input states in favor of the definition of said one or more of said input states that achieves the lowest idle power consumption when said input state vector comprising said one or more input states in accordance with said definition is applied to said circuit inputs.

7. The apparatus of claim 1, in which said conflict resolving module is operable to resolve said any conflict in the definition of said one of more of said input states by a process comprising:

defining said one of said sets of input states as an aggregate input state set; and

performing, for each remaining one of said sets of input states as a current input state set, a sequence comprising;

resolving any conflict in the definitions of any one or more of the input states in said aggregate input state set and said current input state set in favor of the definition that achieves the lowest idle power consumption when said current input state set and said aggregate input state set comprising said one or more of said input states in accordance with said definition are applied to respective ones of said circuit inputs, and

inserting said current state set into said aggregate state set to form a new aggregate input state set for use in the next performing of said sequence, said new aggregate input state set comprising said one or more of said input states in accordance with said definition.

8. The apparatus of claim 1, in which said conflict resolution module comprises:

an idle power consumption indicator coupled to said input state set determining module and configured to indicate respective idle power consumptions respectively achieved by applying possible input state vectors each comprising said one or more of said input states in accordance with a different one of said definitions to said circuit inputs; and

a lower idle power consumption identifier coupled to said idle power consumption indicator and configured to identify the lowest of said idle power consumptions and the corresponding definition of said one or more of said input states.

9. The apparatus of claim 1, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types; and

said idle power assessor comprises a permutation module configured to identify a logically-permissible input connection alteration applicable to each of one or more of said circuit elements, said logically-permissible input connection alteration reducing said lowest-allowable idle power state of said circuit element when said digital circuit is in said idle state.

10. A method for defining an input state vector for application to the circuit inputs of a digital circuit to achieve low power consumption when said digital circuit is in an idle state, said method comprising:

performing independent determinations each defining a respective set of the input states of said input state vector; and

resolving any conflict in the definitions of any one or more of said input states in favor of a definition of said one or more of said input states that achieves the lowest idle power consumption when said input state vector comprising said one or more of said input states in accordance with said definition is applied to said circuit inputs of said digital circuit in said idle state.

11. The method of claim 10, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types;

the method additionally comprises accessing stored idle power values including idle power values for each said circuit element type, said idle power values for said circuit element type corresponding to different states of the inputs of a circuit element of said circuit element type; and

in said performing, each said determination comprises determining from said stored idle power values, for each said circuit element in the segment of said digital circuit subject to said determination, states of the inputs of said circuit element that would set said circuit element to a lowest-allowable idle power state when said digital circuit is in said idle state, said determining accounting for logic constraints of said segment of said digital circuit, said states determined for ones of said inputs that constitute respective ones of said circuit inputs defining said respective set of said input states.

12. The method of claim 10, in which:

said performing comprises;

performing a first determination defining first ones of said input states, said first ones of said input states constituting a first set of said input states of said input state vector, and

performing a second determination, independent of said first determination, defining second ones of said input states, said second ones of said input states constituting a second set of said input states of said input state vector, said second determination and said first determination providing conflicting definitions of one of said input states; and

said resolving comprises resolving said conflict in said definitions of said one of said input states in favor of the definition of said one of said input states that achieves the lower idle power consumption when said input state vector comprising said one of said input states in accordance with said definition is applied to said circuit inputs.

13. The method of claim 10, in which:

said method additionally comprises dividing said digital circuit into segments; and

said performing comprises performing said determinations on different ones of said segments.

14. The method of claim 10, wherein said segments comprise fan-in cones.

15. The method of claim 10, in which said resolving comprises:

indicating respective idle power consumptions achieved by applying possible input state vectors each comprising said one or more of said input states in accordance with a different one of said definitions to said circuit inputs; and

identifying the lowest of said idle power consumptions and the corresponding definition of said one or more of said input states.

16. The method of claim 10, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types; and

said method additionally comprises identifying a logically-permissible input connection applicable to each of one or more of said circuit elements, said logically-permissible input connection alteration reducing said lowest-allowable idle power state of said circuit element when said digital circuit is in said idle state.

17. The method of claim 10, in which:

in said performing, conflict exists in the definitions of no more than one of said input states; and

said resolving comprises resolving said conflict in the definition of said one of said input states in favor of the definition of said one of said input states that achieves the lower power consumption when said input state vector comprising said one of said input states in accordance with said definition is applied to said circuit inputs.

18. The method of claim 10, in which said resolving comprises resolving said any conflict in the definitions of at least two of said input states in favor of the combination of said at least two of said input states that achieves the lowest idle power consumption when said input state vector comprising said at least two of said input states in accordance with said combination is applied to said circuit inputs.

19. The method of claim 10, in which said resolving comprises resolving said any conflict in the definitions of said one or more of said input states in favor of the definition of said one or more of said input states that achieves the lowest idle power consumption when said input state vector comprising said one or more input states in accordance with said definition is applied to said circuit inputs.

20. The method of claim 10, in which said resolving comprises:

defining said one of said sets of input states as an aggregate input state set; and

performing, for each remaining one of said sets of input states as a current input state set, a sequence comprising;

resolving any conflict in the definitions of any one or more of the input states in said aggregate input state set and said current input state set in favor of the definition that achieves the lowest idle power consumption when said current input state set and said aggregate input state set comprising said one or more of said input states in accordance with said definition are applied to respective ones of said circuit inputs, and

inserting said current state set into said aggregate state set to form a new aggregate input state set for use in the next performing of said sequence, said new aggregate input state set comprising said one or more of said input states in accordance with said definition.

21. The method of claim 20, in which

said one of said sets of input states is defined by a first-performed one of said determinations;

and

said sequence is performed on each of said remaining ones of said sets of input states in the order in which the determinations that defined said ones of said remaining ones were performed.

22. The method of claim 20, in which said resolving said any conflict in said definitions of said one or more of said input states in said current input state set and said aggregate input state set comprises resolving said conflict in favor of the combination of said one or more of said input states that achieves the lowest idle power consumption when said current state set and said aggregate state set comprising said one or more of said input states in accordance with said combination are applied to said circuit inputs.

23. The method of claim 20, in which said resolving said any conflict in said definitions of said one or more input states in said current input state set and said previous input state set comprises resolving said conflict in favor of the definition of said one or more of said input states that achieves the lowest idle power consumption when said current state set and said aggregate state set comprising said one or more input states in accordance with said definition are applied to said circuit inputs.

24. A computer-readable medium having stored thereon computer-readable instructions for causing a computer to perform a method for defining an input state vector for application to the circuit inputs of a digital circuit to achieve low power consumption when said digital circuit is in an idle state, said method comprising:

performing independent determinations each defining a respective set of the input states of said input state vector; and

resolving any conflict in the definitions of any one or more of said input states in favor of a definition of said one or more of said input states that achieves the lowest idle power consumption when said input state vector comprising said one or more of said input states in accordance with said definition is applied to said circuit inputs of said digital circuit in said idle state.

25. The computer-readable medium of claim 24, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types;

said method additionally comprises accessing stored idle power values including idle power values for each one of said circuit element types, said idle power values for said one of said circuit element types corresponding to different states of the inputs of a circuit element of said one of said circuit element types; and

in said performing, each said determination comprises determining from said stored idle power values, for each said circuit element in the segment of said digital circuit subject to said determination, states of the inputs of said circuit element that would set said circuit element to a lowest-allowable idle power state when said digital circuit is in said idle state, said determining accounting for logic constraints of said segment of said digital circuit, said states determined for ones of said inputs that constitute respective ones of said circuit inputs defining said respective set of said input states.

26. The computer-readable medium of claim 24, in which:

said performing comprises;

performing a first determination defining first ones of said input states, said first ones of said input states constituting a first set of said input states of said input state vector, and

performing a second determination, independent of said first determination, defining second ones of said input states, said second ones of said input states constituting a second set of said input states of said input state vector, said second determination and said first determination providing conflicting definitions of one of said input states; and

said resolving comprises resolving said conflict in the definitions of said one of said input states in favor of the definition of said one of said input states that achieves the lower power consumption when said input state vector comprising said one of said input states in accordance with said definition is applied to said circuit inputs.

27. The computer-readable medium of claim 24, in which:

said method additionally comprises dividing said digital circuit into segments; and

said performing comprises performing said determinations on different ones of said segments.

28. The computer-readable medium of claim 27, wherein said segments are fan-in cones.

29. The computer-readable medium of claim 24, in which said resolving comprises resolving said any conflict in the definitions of at least two of said input states in favor of the combination of said at least two of said input states that achieves the lowest idle power consumption when said input state vector comprising said at least two of said input states in accordance with said combination is applied to said circuit inputs.

30. The computer-readable medium of claim 24, in which said resolving comprises resolving said any conflict in the definitions of said one or more of said input states in favor of the definition of said one or more of said input states that achieves the lowest idle power consumption when said input state vector comprising said one or more input states in accordance with said definition is applied to said circuit inputs.

31. The computer-readable medium of claim 24, in which said resolving comprises:

defining said one of said sets of input states as an aggregate input state set; and

performing, for each remaining one of said sets of input states as a current input state set, a sequence comprising;

resolving any conflict in the definitions of any one or more of the input states in said aggregate input state set and said current input state set in favor of the definition that achieves the lowest idle power consumption when said current input state set and said aggregate input state set comprising said one or more of said input states in accordance with said definition are applied to respective ones of said circuit inputs, and

inserting said current state set into said aggregate state set to form a new aggregate input state set for use in the next performing of said sequence, said new aggregate input state set comprising said one or more of said input states in accordance with said definition.

32. The computer-readable medium of claim 24, in which said resolving comprises:

indicating respective idle power consumptions respectively achieved by applying possible input state vectors each comprising said one or more of said input states in accordance with a different one of said definitions to said circuit inputs; and

identifying the lowest of said idle power consumptions and the corresponding definition of said one or more of said input states.

33. The computer-readable medium of claim 24, in which:

said digital circuit comprises one or more circuit elements of respective circuit element types; and

said method additionally comprises identifying a logically-permissible input connection applicable to each of one or more of said circuit elements, said logically-permissible input connection alteration reducing said lowest-allowable idle power state of said circuit element when said digital circuit is in said idle state.