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Method and apparatus for writing data between fast and slow clock domains

  • US 7,085,952 B2
  • Filed: 06/10/2002
  • Issued: 08/01/2006
  • Est. Priority Date: 09/14/2001
  • Status: Expired due to Fees
First Claim
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1. In an implantable medical device of the type performing monitoring of a physiologic state and/or therapy delivery under the control of a system comprising a processor that is clocked by a fast clock invoked when a prescribed event occurs and hardware that performs certain device operations and is clocked by a slow clock that is always on, a method for writing data from the processor to the hardware comprising:

  • providing the slow clock;

    detecting a prescribed event requiring operation of the processor;

    turning on the fast clock to enable operation of the processor;

    determining if a bit is to be written from the processor to a register of the hardware;

    pausing the fast clock to the processor until a next rising edge associated with the slow clock when a bit is to be written to the hardware register;

    writing the bit to the register of the hardware upon a slow clock transition while the fast clock to the processor is paused; and

    starting the fast clock at the next rising edge associated with the slow clock to resume operation of the processor.

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