Method and apparatus for writing data between fast and slow clock domains

• US 7,085,952 B2
• Filed: 06/10/2002
• Issued: 08/01/2006
• Est. Priority Date: 09/14/2001
• Status: Expired due to Fees

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Huelskamp, Paul J.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Suryawanshi, Suresh K
• Application Number:
  US10/167,749
• Publication Number:
  US 20030056137A1
• Time in Patent Office: 1,513 Days
• Field of Search: 713/600, 713/400, 713/375, 713/322, 713/320, 607/16, 607/60, 607/2, 711/103
• US Class Current: 713/600
• CPC Class Codes: A61N 1/372 Arrangements in connection with the implantation of stimulators
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for writing data efficiently between a fast clock domain and a slow clock domain. In one embodiment, a processor that performs firmware routines is clocked by a fast clock that is turned on when a prescribed event occurs to operate in the fast clock domain in conjunction with hardware that performs certain device operations that is clocked by a slow clock that is always on to operate in a slow clock domain. Writing data from the processor to the hardware involves determining if a bit is to be written to a register of the slow clock domain in synchrony with a transition of the slow clock, stopping the fast clock to pause operation of the processor, writing the bit to the register of the slow clock domain upon a succeeding slow clock transition, and starting the fast clock to resume operation of the processor.

Claims

1. In an implantable medical device of the type performing monitoring of a physiologic state and/or therapy delivery under the control of a system comprising a processor that is clocked by a fast clock invoked when a prescribed event occurs and hardware that performs certain device operations and is clocked by a slow clock that is always on, a method for writing data from the processor to the hardware comprising:

providing the slow clock;

detecting a prescribed event requiring operation of the processor;

turning on the fast clock to enable operation of the processor;

determining if a bit is to be written from the processor to a register of the hardware;

pausing the fast clock to the processor until a next rising edge associated with the slow clock when a bit is to be written to the hardware register;

writing the bit to the register of the hardware upon a slow clock transition while the fast clock to the processor is paused; and

starting the fast clock at the next rising edge associated with the slow clock to resume operation of the processor.

2. The method of claim 1, further comprising the step of turning off the fast clock upon a shut down request.