Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack

• US 7,085,979 B2
• Filed: 05/22/2003
• Issued: 08/01/2006
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chan-Yong, Kim, Eui-Seung, Jun, Sang-Joo
• Primary Examiner(s): Ton, David
• Application Number:
  US10/443,427
• Publication Number:
  US 20030226082A1
• Time in Patent Office: 1,167 Days
• Field of Search: 365/45, 327/74, 327/142, 327/108, 361/90, 714/734, 714/733
• US Class Current: 714/734
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

Claims

1. A voltage-glitch detection circuit of an integrated circuit chip, comprising:

a first voltage dividing circuit for dividing an operation voltage into a first voltage and a second voltage dividing circuit for dividing the operation voltage into a second voltage;

a voltage comparator having a first input terminal and a second input terminal coupled to the first and second voltage, respectively and generating a first level comparison signal at an output terminal depending on a voltage difference between the first and second voltages; and

a capacitor coupled to at least one of the two voltage dividing circuits and reversing a polarity of the voltage difference between the first voltage and second voltage when a glitch is generated at the operation voltage.

2. A voltage-glitch detection circuit of an integrated circuit chip, comprising:

a first voltage dividing circuit and a second voltage dividing circuit, each having at least two resistors coupled in series between an operation voltage for driving the integrated circuit chip and a ground;

a voltage comparator having a first input terminal coupled to a first node between the two resistors of the first voltage dividing circuit to receive a first node voltage and a second input terminal coupled to a second node between the two resistors of the second voltage dividing circuit to receive a second node voltage, the voltage comparator for generating a first comparison signal at an output terminal depending on a voltage difference between the first and second input terminals;

a buffer for buffering the first comparison signal to output a first detection signal; and

a capacitor connecting one of the first and second nodes to ground,

wherein the second voltage dividing circuit has a capacitor connected to the second node and the buffer includes two successive inverters;

wherein the first comparison signal is a logic high signal when the second node voltage is higher than the first node voltage; and

wherein if a glitch occurs to temporarily increase the chip operation voltage, the first comparison signal of the comparator transitions from a logic high signal to a logic low signal and a logic high detection signal is generated by the buffer to detect the glitch.

3. A voltage-glitch detection circuit of an integrated circuit chip, comprising:

a first voltage dividing circuit and a second voltage dividing circuit, each having at least two resistors coupled in series between an operation voltage for driving the integrated circuit chip and a ground;

a voltage comparator having a first input terminal coupled to a first node between the two resistors of the first voltage dividing circuit to receive a first node voltage and a second input terminal coupled to a second node between the two resistors of the second voltage dividing circuit to receive a second node voltage, the voltage comparator for generating a first comparison signal at an output terminal depending on a voltage difference between the first and second input terminals;

a buffer for buffering the first comparison signal to output a first detection signal; and

a capacitor connecting one of the first and second nodes to ground.

wherein the second voltage dividing circuit includes a capacitor connected between ground and the second node;

wherein the first comparison signal is a logic low signal when the second node voltage is lower than the first node voltage; and

wherein if a glitch occurs to temporarily decrease the chip operation voltage, the first comparison signal of the comparator transitions from a logic low signal to a logic high signal and a logic low detection signal is generated by the buffer to signal glitch detection.

4. A voltage-glitch detection circuit of an integrated circuit chip, comprising:

a first voltage dividing circuit and a second voltage dividing circuit, each having at least two resistors coupled in series between an operation voltage for driving the integrated circuit chip and a ground;

a voltage comparator having a first input terminal coupled to a first node between the two resistors of the first voltage dividing circuit to receive a first node voltage and a second input terminal coupled to a second node between the two resistors of the second voltage dividing circuit to receive a second node voltage, the voltage comparator for generating a first comparison signal at an output terminal depending on a voltage difference between the first and second input terminals;

a buffer for buffering the first comparison signal to output a first detection signal; and

a capacitor connecting one of the first and second nodes to ground, further comprising;

a third voltage dividing circuit having at least two resistors coupled in series between the operation voltage source and ground;

a second comparator having a first input terminal coupled to a third node between the two resistors of the third voltage dividing circuit to receive a third node voltage and a second input terminal to receive the second node voltage, the second comparator for generating a second comparison signal at an output terminal depending on a voltage difference between the two input terminals of the second comparator;

a second buffer for buffering the second comparison signal to output a second detection signal, the second buffer having a value between the first node voltage and the third node voltage; and

AND operation means for performing an AND operation of the two detection signal to be outputted,

wherein the second voltage dividing circuit includes a second capacitor.

5. The voltage-glitch detection circuit as recited in claim 4, wherein the third node voltage is higher than the first node voltage, the first buffer has two inverters, and the second buffer has one inverter.

6. The voltage-glitch detection circuit as recited in claim 5, further comprising:

a first grounded capacitor disposed at the first node; and

a third grounded capacitor disposed at the second node,

wherein capacitance of the first and third grounded capacitors are lower than the capacitance of the second capacitor.

7. The voltage-glitch detection circuit as recited in claim 4,

wherein the third node voltage is higher than the first node voltage, the first buffer has two inverters serially coupled to each other, and the second buffer has one inverter.

8. A voltage-glitch detection circuit of an integrated circuit chip, comprising:

first and second voltage dividing means for dividing a chip operation voltage for driving the integrated circuit chip into first and second voltages having a first voltage difference by using at least two resistors sequentially coupled in series between the chip operation voltage and a ground;

first voltage comparing means having a first input terminal coupled to a first node between the two resistors of the first voltage dividing means to receive a first node voltage, a second input terminal coupled to a second node between the two resistors of the second voltage dividing means to receive a second node voltage, and a first comparator output terminal to output a first comparison signal depending on the first voltage difference;

first buffering means for receiving the first comparison signal and outputting a first detection signal to a first buffer output terminal, the first detection signal being obtained by buffering the first comparison signal;

a first capacitor disposed between the first node and a ground; and

a second capacitor disposed between the second node and the ground,

wherein capacitance of the first capacitor is so different from that of the second capacitor that when a glitch occurs at the operation voltage to change the first node voltage and the second node voltage into a first glitch voltage and a second glitch voltage respectively, a second voltage difference between the two glitch voltages has an opposite sign to the first voltage difference.

9. The voltage-glitch detection circuit as claimed in claim 8, wherein capacitance of the second capacitor is higher than that of the first capacitor, the first buffering means has two inverters serially coupled to the first comparator output terminal, the first comparator output terminal outputs a logic high first comparison signal and the first buffer output terminal outputs a logic high first detection signal through the first buffering means, and;

wherein if a high glitch attack occurs to increase the chip operation voltage, the first voltage becomes higher than the second glitch voltage, so that the first comparator terminal outputs a logic low first comparison signal and the first buffer output terminal outputs a logic low first detection signal through the first buffering means to detect a high glitch attack.

10. The voltage-glitch detection circuit as recited in claim 8, wherein the second capacitor has a higher capacitance than the first capacitor, the first buffering means has one inverter coupled to the first comparator output terminal, the first comparator output terminal outputs a logic low first comparison signal and the first buffer output terminal outputs a logic high first detection signal through the first buffering means because the first voltage is higher than the second voltage;

and

wherein if a low glitch occurs to decrease the chip operation voltage, the first voltage becomes lower than the second voltage, so that the first comparator output terminal outputs a logic high first comparison signal and the first buffer output terminal outputs a logic low first detection signal through the first buffering means to detect the low glitch attack.

11. The voltage-glitch detection circuit as recited in claim 8, further comprising:

third voltage dividing means for dividing the operation voltage into a third voltage by using the two resistors serially coupled between the detector input terminal and the ground, the second voltage having a value between the first voltage and the third voltage, and the second and third voltages having a second voltage difference;

second voltage dividing means having a first input terminal coupled to a third node between the two resistors of the third voltage dividing means to receive a third node voltage, a second input terminal to receive the second voltage, and a second comparator output terminal to output a second comparison signal depending on the second voltage difference;

second buffering means for inputting the second comparison signal and outputting a second detection signal to a second buffer output terminal, the second detection signal being obtained by buffering the second comparison signal; and

AND operation means for performing an AND operation of the first and second detection signals to be outputted,

wherein the third voltage dividing means includes a third capacitor disposed between the third node and the ground, capacitance of the third capacitor being substantially equal to that of the first capacitor.

12. The voltage-glitch detection circuit as recited in claim 11, wherein the first voltage is supplied as a detection voltage of the first voltage comparing means, the third voltage is supplied as a detection voltage of the second comparing means, the second voltage is supplied as a reference voltage of the first and second voltage comparing means, the third voltage is higher than the first voltage, the first buffering means has two inverters sequentially coupled in series to the first comparator output terminal, and the second buffering means has one inverter coupled to the first comparator output terminal.

13. The voltage-glitch detection circuit as recited in claim 12, wherein capacitance of the second capacitor is higher than capacitances of the first and third capacitors.

14. The voltage-glitch detection circuit as recited in claim 12, wherein capacitance of the second capacitor is lower than capacitances of the first and third capacitors.

15. A smart card embedding a semiconductor integrated circuit chip having a central processing unit (CPU) to detect both a low glitch and a high glitch, the smart card comprising:

a detector input terminal receiving an operation voltage for driving the integrated circuit chip;

first, second, and third voltage dividers for dividing first, second, and third voltages by using the operation voltage supplied to the detector input terminal and two resistors serially coupled to the detector input terminal and a ground respectively, the first voltage being lower than the second voltage and the second voltage being lower than the third voltage;

a first voltage comparator having a first comparator first input terminal coupled to a first node between the two resistors of the first voltage divider to receive a first node voltage, a first comparator second input terminal coupled to a second node between the two resistors of the second voltage divider to receive a second node voltage, and a first comparator output terminal to output a logic high comparison signal depending on a first voltage difference that is a difference between the second and first voltages;

a second voltage comparator having a second comparator first input terminal coupled to a third node of the two resistors of the third voltage divider to receive the third voltage of the third node, a second comparator second input terminal coupled to the second node to receive the second node voltage, and a second comparator output terminal to output a logic low comparison signal depending on a second voltage difference that is a difference between the second and third voltages;

first buffering means for buffering the logic high comparison signal of the first comparator output terminal to output a logic high first buffering signal to a first buffer output terminal;

second buffering means for buffering the logic low comparison signal of the second comparator output terminal to output a logic high second buffering signal to a second buffer output terminal;

AND operation means for performing an AND operation of the first and second buffering signals of the first and second buffer output terminals to output a logic high detection signal;

a detector output terminal receiving the logic high detection signal of the AND operation means; and

a first capacitor disposed between the first node and a ground, a second capacitor disposed between the second node and a ground, and a third capacitor disposed between the third node and the ground,

wherein capacitances of the first and third capacitors are substantially equal to each other but different from capacitance of the second capacitor.

16. The smart card as recited in claim 15, wherein the first buffering means has two inverters successively coupled in series to the first comparator output terminal and the second buffering means has one inverter couple to the second comparator output terminal;

and

wherein the capacitance of the second capacitor is higher than the capacitance of the first and third capacitors.

17. The smart card as recited in claim 15, wherein the first buffering means has two inverters successively coupled in series to the first comparator output terminal and the second buffering means has one inverter couple to the second comparator output terminal;

and

wherein the capacitance of the second capacitor is lower than the capacitance of the first and third capacitors.

18. A method for securing an integrated circuit device from an external glitch attack, comprising:

generating a reference voltage and a detection voltage by using an operation voltage for driving the integrated circuit device, the reference voltage being impervious to a glitch variation as compared to the detection voltage;

comparing the reference voltage with the detection voltage to detect a glitch attack occurring at the operation voltage of the integrated circuit device; and

resetting the integrated circuit device when the glitch attack is detected.