Electronic circuit design method, simulation apparatus and computer-readable storage medium

• US 7,086,018 B2
• Filed: 06/09/2003
• Issued: 08/01/2006
• Est. Priority Date: 06/19/2002
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ito, Noriyuki
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): TO, TUYEN P
• Application Number:
  US10/456,679
• Publication Number:
  US 20030237066A1
• Time in Patent Office: 1,149 Days
• Field of Search: 716/4, 716/5
• US Class Current: 716/112
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

An electronic circuit designing method analyzes noise with respect to a wiring pair, and automatically corrects the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise.

Claims

1. An electronic circuit designing method comprising:

an analyzing step analyzing noise with respect to a wiring pair; and

a correcting step automatically correcting the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing step,

wherein said analyzing step detects a noise error if a parallel wiring length for which adjacent wirings of a victim net and an aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net exceeds a tolerable parallel wiring length L described by;

L≦

f6(Ra, Rv, Cc)

 

where Ra denotes an aggressor side driver resistance, Rv denotes a victim side driver resistance, and Cc denotes a coupling capacitance between two adiacent wirings.

2. The electronic circuit designing method as claimed in claim 1, wherein said correcting step creates a wiring rule based on the spacing which is determined.

3. The electronic circuit designing method as claimed in claim 2, further comprising:

a wiring step carrying out a wiring, with the spacing which prevents generation of the noise error, according to the wiring rule, using an automatic wiring software.

4. The electronic circuit designing method as claimed in claim 1, wherein said analyzing step outputs, upon detecting the noise error, a check result list including an aggressor net, a victim net, a tolerable noise value of the victim net, a noise value of the aggressor net, and a parallel wiring length for which adjacent wirings of the victim net and the aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net.

5. The electronic circuit designing method as claimed in claim 4, wherein said correcting step includes:

sorting the check result list;

determining a priority with which the spacing between the aggressor net and the victim net is to be provided at the adjacent wiring portion;

determining a spacing value of the spacing; and

outputting the wiring rule including at least the spacing value which is determined.

6. The electronic circuit designing method as claimed in claim 5, wherein said wiring rule includes a net name, a tolerable spacing value by which an adjacent net may approach each net, and/or the priority.

7. An electronic circuit designing method comprising:

an analyzing step analyzing noise with respect to a wiring pair; and

a correcting step automatically correcting the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing step,

wherein said analyzing step outputs, upon detecting the noise error, a check result list including an aggressor net, a victim net, a tolerable noise value of the victim net, a noise value of the aggressor net, and a parallel wiring length for which adjacent wirings of the victim net and the aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net

wherein said correcting step includes;

sorting the check result list;

determining a priority with which the spacing between the aggressor net and the victim net is to be provided at the adiacent wiring portion;

determining a spacing value of the spacing; and

outputting the wiring rule including at least the spacing value which is determined,

wherein said correcting step sorts the check result list based on the victim net and an accumulated length of parallel wirings for the victim net, the victim net and an appearing frequency of the victim net, the aggressor net and an appearing frequency of the aggressor net, or an aggressor/victim net which appears as both the victim net and the aggressor net and an appearing frequency of the aggressor/victim net.

8. A computer-readable storage medium which stores a program for causing a computer to design an electronic circuit, said program comprising:

an analyzing procedure causing the computer to analyze noise with respect to a wiring pair; and

a correcting procedure causing the computer to automatically correct the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing procedure,

wherein said analyzing procedure causes the computer to detect a noise error if a parallel wiring length for which adjacent wirings of a victim net and an aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net exceeds a tolerable parallel wiring length L described by;

L≦

f6(Ra, Rv, Cc)

 

where Ra denotes an aggressor side driver resistance, Rv denotes a victim side driver resistance, and Cc denotes a coupling capacitance between two adjacent wirings.

9. The computer-readable storage medium as claimed in claim 8, wherein said correcting procedure causes the computer to create a wiring rule based on the spacing which is determined.

10. The computer-readable storage medium as claimed in claim 9, wherein said program further comprising:

a wiring procedure causing the computer to carry out a wiring, with the spacing which prevents generation of the noise error, according to the wiring rule, using an automatic wiring software.

11. The computer-readable storage medium as claimed in claim 8, wherein said analyzing procedure causes the computer to output, upon detecting the noise error, a check result list including an aggressor net, a victim net, a tolerable noise value of the victim net, a noise value of the aggressor net, and a parallel wiring length for which adjacent wirings of the victim net and the aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net.

12. The computer-readable storage medium as claimed in claim 11, wherein said correcting procedure includes causing the computer to:

sort the check result list;

determine a priority with which the spacing between the aggressor net and the victim net is to be provided at the adjacent wiring portion;

determine a spacing value of the spacing; and

output the wiring rule including at least the spacing value which is determined.

13. The computer-readable storage medium as claimed in claim 12, wherein said wiring rule includes a net name, a tolerable spacing value by which an adjacent net may approach each net, and/or the priority.

14. A computer-readable storage medium which stores a program for causing a computer to design an electronic circuit, said program comprising:

an analyzing procedure causing the computer to analyze noise with respect to a wiring pair; and

a correcting procedure causing the computer to automatically correct the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing procedure

wherein said analyzing procedure causes the computer to output, upon detecting the noise error, a check result list including an aggressor net, a victim net, a tolerable noise value of the victim net, a noise value of the aggressor net, and a parallel wiring length for which adjacent wirings of the victim net and the aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net

wherein said correcting procedure includes causing the computer to;

sort the check result list;

determine a priority with which the spacing between the aggressor net and the victim net is to be provided at the adjacent wiring portion;

determine a spacing value of the spacing; and

output the wiring rule including at least the spacing value which is determined,

wherein said correcting procedure causes the computer to sort the check result list based on the victim net and an accumulated length of parallel wirings for the victim net, the victim net and an appearing frequency of the victim net, the aggressor net and an appearing frequency of the aggressor net, or an aggressor/victim net which appears as both the victim net and the aggressor net and an appearing frequency of the aggressor/victim net.

15. A simulation apparatus for designing an electronic circuit, comprising:

analyzing means for analyzing noise with respect to a wiring pair; and

correcting means for automatically correcting the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise by said analyzing means,

wherein said analyzing step detects a noise error if a parallel wiring length for which adjacent wirings of a victim net and an aggressor net are parallel to each other in an adjacent wiring portion between the victim net and the aggressor net exceeds a tolerable parallel wiring length L described by;

L≦

f6(Ra, Rv, Cc)

 

where Ra denotes an aggressor side driver resistance, Rv denotes a victim side driver resistance, and Cc denotes a coupling capacitance between two adjacent wirings.