Processor unit for executing event processes in real time without causing process interference

• US 7,086,056 B2
• Filed: 03/15/2002
• Issued: 08/01/2006
• Est. Priority Date: 03/19/2001
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Fukushima, Toshiyuki
• Primary Examiner(s): An, Meng-Al T.
• Assistant Examiner(s): To, Jennifer N.
• Application Number:
  US10/097,834
• Publication Number:
  US 20020133531A1
• Time in Patent Office: 1,600 Days
• Field of Search: 718100-108, 719/319, 711144-159, 711/121, 711/207, 710/40, 710 56-267, 700/245, 701 35-114, 714/15, 714/53
• US Class Current: 718/102
• CPC Class Codes: G06F 11/0715 in a system implementing multitasking multitasking per se G06F9/46
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A processor unit executes a failure detection program for a vehicle. The failure detection program includes a first failure detection process of a high priority level, a second failure detection process of a moderate priority level and a memory manipulation process of a low priority level. Each of the failure detection processes requests memory manipulation by generating an event as the need arises. When the memory manipulation process is activated, it performs the requested memory manipulation in the same order as the memory manipulation is requested so that execution of memory manipulation requested by one of the failure detection processes is not interrupted by execution of memory manipulation requested by the other of the failure detection processes. However, each of the failure detection processes itself can be executed interrupting the execution of memory manipulation process because of its higher priority level.

Claims

1. A processor unit for implementing a series of functions comprising a program for implementing said series of functions, said program comprising a plurality of at least three processes,

wherein said program is executed by switching between said plurality of at least three processes based on priority levels assigned to individual ones of said plurality of at least three processes, and at least two processes of different respective priority levels manipulate a common memory area,

wherein said program includes a memory manipulation process for implementing memory read/write operations as one of said plurality of at least three processes,

wherein each of said plurality of at least three processes except said memory manipulation process requests memory manipulation by giving a memory read/write instruction as a need arises during execution of said program, and said memory manipulation process performs the requested memory manipulation in response to said instruction when activated,

wherein a specific priority level is assigned to said memory manipulation process so that execution of memory manipulation requested by a first process is not interrupted by execution of memory manipulation requested by a second process irrespective of priority levels of said first and second processes, and

wherein said instruction includes identification information for identifying a process that requests the memory manipulation.

2. A processor unit as in claim 1, wherein the requested memory manipulations are performed by said memory manipulation process in the same order as they are requested by other processes.

3. A processor unit as in claim 1,

wherein said series of functions is provided for failure diagnosis in an on-vehicle device, and

wherein said memory manipulation process performs the requested memory manipulation on failure diagnosis information.

4. A processor unit as in claim 3,

wherein memory is allocated for respective pieces of said failure diagnosis information on a bit-by-bit basis, and

wherein said memory manipulation process manipulates said failure diagnosis information stored in said common memory area on a byte basis.

5. A processor unit as in claim 1, wherein said memory manipulation process identifies a requester process based on said identification information, and further identifies a portion of the memory area that corresponds to the identified requester.

6. A stored program medium containing a computer program for implementing a series of functions comprising a plurality of processes,

wherein said program is executed by switching between said plurality of processes based on priority levels assigned to individual ones of said plurality of processes, and at least two processes of different respective priority levels manipulate a common memory area,

wherein said program includes a memory manipulation process for implementing memory read/write operations as one of said plurality of processes,

wherein each of said plurality of processes except said memory manipulation process requests memory manipulation by giving a memory read/write instruction as a need arises during execution of said program, and said memory manipulation process performs the requested memory manipulation in response to said instruction when activated, and

wherein a priority level is assigned to said memory manipulation process so that execution of memory manipulation requested by a first process is not interrupted by execution of memory manipulation requested by a second process irrespective of priority levels of said first and second processes, and

wherein said instruction includes identification information for identifying the process that requests the memory manipulation.

7. A processor unit executes a plurality of processes implementing a series of functions, wherein each of the plurality processes is assigned a priority level, and is executed based on the assigned priority level, the processor unit comprising:

at least a first and a second process included in the plurality of processes.

wherein the first process has a first priority level and the second process has a second priority level different from the first priority level, and

wherein each of the at least two processes provides, while being executed, a memory manipulation instruction requesting a memory read/write operation in an area of memory; and

a third process is included in the plurality of processes and has a third priority level lower than both the first priority level and the second priority level,

wherein the third process performs the requested memory manipulation during its execution based on the third priority level independently of the priority level of the requester, and

wherein the memory manipulation instruction of includes identification information.

8. A processor unit as in claim 7,

wherein requested memory manipulations are performed by the third process in the same order as they were requested.

9. A processor unit as in claim 7,

wherein the series of functions is provided for failure diagnosis in an on-vehicle device, and

wherein the third process performs requested memory manipulation of failure diagnosis information based on a memory manipulation instruction given by a requester.

10. A processor unit as in claim 9,

wherein the memory area allocated for respective pieces of the failure information is on a bit-by-bit basis,

wherein the third process manipulates the failure diagnosis information stored in the memory area on a byte-by-byte basis.

11. A processor unit as in claim 7,

wherein the third process identifies the requester process based on the identification information, and further identifies a portion of memory area that corresponds to the identified requester and is to be manipulated.

12. A computer program product in a computer-readable medium for use in implementing a series of functions using a program including a plurality of processes, wherein each of the plurality of processes is assigned a priority level, and is executed based on the assigned priority level, the computer program product comprising:

at least a first process and a second process that are included in the plurality of processes,

wherein the first process has a first priority level and the second process has a second priority level different from the first priority level, and

wherein each of the at least two processes provides, while being executed, a memory manipulation instruction requesting a memory read/write operation in an area of memory; and

a third process is included in the plurality of processes and has a third priority level lower than both the first priority level and the second priority level,

wherein the third process performs the requested memory manipulation during its execution based on the third priority level independently of the priority level of the requester, and

wherein the memory manipulation instructin includes identification information.