Edge arrangements for integrated circuit chips

• US 7,087,452 B2
• Filed: 04/22/2003
• Issued: 08/08/2006
• Est. Priority Date: 04/22/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Leavy, Tom P., Arcot, Binny, He, Jun, Joshi, Subhash M.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/419,759
• Publication Number:
  US 20040212047A1
• Time in Patent Office: 1,204 Days
• Field of Search: 438/68, 438/107, 438/113, 438460-465
• US Class Current: 438/68
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is provided for forming microelectronic devices. This may include providing a wafer device having metallization layers, a plurality of integrated circuits and a channel area provided around each of the integrated circuits. Materials from within each channel area may be removed by etching or by laser to form an air gap around a perimeter of each integrated circuit. Each air gap may prevent cracking and/or delamination problems caused by a subsequent dicing of the wafer device by a wafer saw into a plurality of devices.

Claims

1. A method of dicing a wafer comprising:

providing the wafer including an active area and an inactive area around a perimeter of the active area;

providing a cut path including a metal and a dielectric material in the inactive area and around the perimeter of the active area, wherein a top surface of the cut path includes a pattern of the metal and the dielectric material;

removing, via ablation by the laser, a portion of the cut path to form an air gap; and

cutting through the wafer within the inactive area.

2. The method of claim 1, wherein the pattern comprises a grid of the metal around the dielectric material.

3. The method of claim 1, wherein the pattern comprises a grid of the dielectric material around the metal.

4. The method of claim 1, wherein the pattern comprises strips of the metal and the dielectric material, wherein the strips are parallel to an edge of the active area.

5. The method of claim 1, wherein the pattern comprises strips of the metal and the dielectric material, wherein the strips are perpendicular to an edge of the active area.

6. The method of claim 1, further comprising:

designing the pattern based on the laser.

7. The method of claim 1, further comprising:

designing the pattern based on the metal and the dielectric material.

8. The method of claim 1, further comprising:

designing the pattern based on the laser.

9. The method of claim 1, further comprising:

providing a metal guard between the active area and the laser cut path.

10. A method of dicing a wafer comprising:

providing the wafer including a channel area between two active areas, wherein the channel area includes a dielectric material between two metal walls on the wafer and a passivation layer over the dielectric material and the metal walls;

forming a mask over the passivation layer that includes an opening over the dielectric material;

etching, via an isotropic etch, the dielectric material to form an air gap, such that the metal walls remain; and

cutting through the wafer in the channel.

11. The method of claim 10, wherein the metal walls comprise smooth sidewalls.

12. The method of claim 10, wherein the metal walls comprise sidewalls having a zigzag type of vertical pattern.

13. The method of claim 10, wherein the isotropic etch comprises a wet etch process.

14. The method of claim 10, wherein the isotropic etch comprises a dry etch process.

15. The method of claim 10, further comprising:

etching the passivation layer to expose the dielectric material.

16. The method of claim 10, further comprising a metal base and a second dielectric material between the two metal walls, wherein the second dielectric material is over the wafer and the metal base is over the second dielectric material.

17. The method of claim 10, wherein cutting through the wafer comprises cutting through the wafer between the two metal walls.