Method for forming leadless semiconductor packages

• US 7,087,462 B1
• Filed: 06/07/2005
• Issued: 08/08/2006
• Est. Priority Date: 06/07/2005
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Park, Hyung-Jun, Lee, Yong-Gill, Park, Sang-Bae, Sohn, Chang-Young
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US11/160,070
• Time in Patent Office: 427 Days
• Field of Search: 438111-113, 438/124, 438460-462, 438/689, 257/666, 257/667, 257/676, 257/784, 257/787
• US Class Current: 438/112
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

The present invention includes providing a leadframe including a metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, in which each unit includes a die pad, a plurality of leads, and a plurality of outer dambars, adhering a die to the die pad, forming a plurality of conductive wires to electrically connect bond pads of the die with bond regions of the leads, forming an encapsulation covering the leadframe, forming a patterned photoresist layer on a lower surface of the leadframe to expose a plurality of interval regions and the outer dambars, performing an etching process to expose the metal layer located in the interval regions and the outer dambars, cutting off the metal layer located in the interval regions by a half cutting process, and performing a singulation process to singulate the units.

Claims

1. A method for forming leadless semiconductor packages comprising:

providing a leadframe comprising a first metal layer formed on an upper surface of the leadframe and a plurality of units in an array arrangement, wherein each of the units comprises a die pad, a plurality of leads comprising a plurality of bond regions, and a plurality of outer dambars disposed in a periphery of each of the units;

adhering a lower surface of a die to the first metal layer of the die pad, wherein a plurality of bond pads are disposed on an upper surface of the die;

forming a plurality of conductive wires to electrically connect the bond pads with the corresponding bond regions of the leads;

forming an encapsulation covering the die, the leads, and the leadframe, wherein the encapsulation exposes lower surfaces of the die pad, the leads, and the outer dambars;

forming a patterned photoresist layer on a lower surface of the leadframe, wherein the patterned photoresist layer exposes a plurality of interval regions of the leads and the outer dambars;

performing an etching process by utilizing the patterned photoresist layer as a mask to expose the first metal layer located in the interval regions and the outer dambars;

removing the patterned photoresist layer;

forming a second metal layer on the lower surfaces of the die pad, the leads, and the outer dambars after removing the patterned photoresist layer;

cutting off the first metal layer located in the interval regions by utilizing a half cutting process to electrically isolate the bond regions; and

performing a singulation process to singulate the units by cutting off the first metal layer and the encapsulation located in the outer dambars.

2. The method for forming leadless semiconductor packages of claim 1, wherein the interval regions are located between the adjacent bond regions.

3. The method for forming leadless semiconductor packages of claim 1, wherein the leads connect to the die pad.

4. The method for forming leadless semiconductor packages of claim 3, wherein the interval regions are located between the bond regions and the adjacent die pad.

5. The method for forming leadless semiconductor packages of claim 1, wherein the units connect together with the outer dambars.

6. The method for forming leadless semiconductor packages of claim 1, wherein the leadframe is composed of copper, iron, or an alloy of copper and iron.

7. The method for forming leadless semiconductor packages of claim 1, wherein the leads connect to the outer dambars.

8. The method for forming leadless semiconductor packages of claim 1, wherein each of the units further comprises a plurality of tie bars connecting the die pad and the outer dambars.

9. The method for forming leadless semiconductor packages of claim 8, wherein each of the units further comprises a plurality of inner dambars connecting the leads serially and the tie bars.

10. The method for forming leadless semiconductor packages of claim 9, wherein the patterned photoresist layer exposes the inner dambars, and the etching process removes the inner dambars simultaneously to expose the first metal layer located in the inner dambars.

11. The method for forming leadless semiconductor packages of claim 10, wherein the half cutting process cuts off the first metal layer located in the inner dambars to electrically isolate the bond regions.

12. The method for forming leadless semiconductor packages of claim 1, wherein the first metal layer is composed of silver.

13. The method for forming leadless semiconductor packages of claim 1 further comprising a step of adhering a tape on the lower surface of the leadframe before forming the encapsulation covering the leadframe, and a step of removing the tape after forming the encapsulation covering the leadframe.

14. The method for forming leadless semiconductor packages of claim 1, wherein the second metal layer is composed of tin or lead.

15. The method for forming leadless semiconductor packages of claim 1, wherein the half cutting process utilizes a saw blade to perform cutting.

16. The method for forming leadless semiconductor packages of claim 1, wherein the leads are in-line leads.

17. The method for forming leadless semiconductor packages of claim 1, wherein the leads are staggered leads.