FinFET SRAM cell using low mobility plane for cell stability and method for forming

• US 7,087,477 B2
• Filed: 11/12/2004
• Issued: 08/08/2006
• Est. Priority Date: 12/04/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Fried, David M., Muller, K. Paul, Mann, Randy W.
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): KRAIG, WILLIAM F
• Application Number:
  US10/987,532
• Publication Number:
  US 20050121676A1
• Time in Patent Office: 634 Days
• Field of Search: 438/982, 438/154, 438197-199, 257/627, 257/255, 257/527
• US Class Current: 438/199
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.

Claims

1. A method of forming a semiconductor device, the method comprising the steps of:

forming a patterned hard mask on a semiconductor substrate, wherein a first portion of the hard mask is oriented in a first direction, and wherein a second portion of the hard mask is oriented in a second direction that differs from the first direction;

anisotropically etching the substrate, using the hard mask as an etching mask, to form a fin body, wherein the fin body has a first portion with a sidewall oriented in the first direction and oriented on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall oriented in the second direction and oriented on a second plane that provides a second carrier mobility, wherein the second carrier mobility differs from the first carrier mobility;

forming a transfer transistor at the first portion of the fin body; and

forming a latch transistor at the second portion of the fin body, wherein the transfer transistor comprises an n-channel transistor and wherein the latch transistor comprises an n-channel transistor, wherein the transfer transistor and the storage transistor are formed as part of a memory cell, and wherein the transfer transistor is coupled to pass data to the storage transistor.

2. The method of claim 1, further comprising selecting the first and second directions such that the first carrier mobility is loss than the second carrier mobility.

3. The method of claim 2, wherein the transfer transistor has a gain, and the latch transistor has a gain, and wherein the transfer transistor gain is less than the latch transistor gain due to the first carrier mobility being less than the second carrier mobility.

4. The method of claim 1, further comprising selecting the first and second directions such that the first plane comprises a {110} plane and the second plane comprises a {100} plane.

5. The method of claim 1, wherein the memory cell comprises an SRAM memory cell.

6. A method of forming a memory cell comprising;

forming a patterned hard mask on a semiconductor substrate, wherein a first portion of the hard mask is oriented in a first direction, and wherein a second portion of the hard mask is oriented in a second direction that differs from the first direction;

anisotropically etching the substrate, using the hard mask as an etching mask, to form a first fin body and a second fin body, wherein the first fin body comprises a first sidewall oriented in the first direction and oriented on a first plane that provides a first carrier mobility, and wherein the second fin body comprises a second sidewall oriented in the second direction and oriented on a second plane that provides a second carrier mobility, wherein the second carrier mobility differs from the first carrier mobility;

providing a first transfer transistor that includes the first fin body having the first sidewall;

providing a second transfer transistor that includes the second fin body having the second sidewall; and

coupling a storage latch to the first and second transfer transistors to receive data from the first and second transfer transistors, wherein the storage latch comprises first and second storage latch transistors, and wherein the first storage latch transistor includes a third fin body having a third sidewall and wherein the second storage latch transistor has a fourth body having a fourth sidewall.

7. The method of claim 6, wherein the third sidewall is oriented on a third crystal plane, and wherein the fourth sidewall is oriented on a fourth crystal plane, and wherein the first, second, third and fourth crystal planes are selected to provide a greater carrier mobility in the first and second storage latch transistors than the carrier mobility in the first and second transfer transistors.

8. The method of claim 7, wherein the first transfer transistor comprises a n-channel transistor and wherein the first plane comprises a {110} plane and wherein the first storage latch transistor comprises an n-channel transistor and wherein the third plane comprises a {100} plane.

9. The method of claim 6, wherein the first transfer transistor, the second transfer transistor, the first storage latch transistor, and the second storage latch transistor each comprise an n-channel transistor.

10. The method of claim 9, wherein the storage latch further comprises a first p-channel transistor and a second p-channel transistor.

11. A method of forming a semiconductor structure comprising:

forming a patterned hard mask on a semiconductor substrate, wherein a first portion of the hard mask is oriented in a first direction, and wherein a second portion of the hard mask is oriented in a second direction that differs from the first direction;

anisotropically etching the substrate, using the hard mask as an etching mask, to form a fin body, wherein the fin body has a first portion with a sidewall oriented in the first direction and oriented on a first plane that provides a first carrier mobility, and wherein the fin body has a second portion with a sidewall oriented in the second direction and oriented on a second plane that provides a second carrier mobility, wherein the second carrier mobility differs from the first carrier mobility;

providing a first transfer transistor at the first portion of the fin body;

providing a latch transistor at the second portion of the fin body; and

providing a second transfer transistor, wherein the latch transistor is disposed between and coupled to the first transfer transistor and the second transfer transistor.

12. The method of claim 11, wherein the first transfer transistor, the second transfer transistor, and the latch transistor each comprise an n-channel transistor.

13. The method of claim 11, farther comprising selecting the first and second directions such that the first carrier mobility is less than the second carrier mobility.

14. The method of claim 13, wherein the first transfer transistor has a gain, wherein the latch transistor has a gain, and wherein the first transfer transistor gain is less than the latch transistor gain due to the first carrier mobility being less than the second carrier mobility.

15. The method of claim 13, wherein the first transfer transistor comprises a portion of a memory cell.

16. The method of claim 15, wherein the memory cell comprises an SRAM memory cell.

17. The method of claim 11, further comprising selecting the first and second directions such that the first plane comprises a {110} plane and the second plane comprises a {100} plane.

18. The method of claim 11, wherein the first transfer transistor and the storage transistor are a part of a memory cell, and wherein the first transfer transistor is coupled to pass data to the storage transistor.