Test arrangement for testing semiconductor circuit chips

• US 7,088,122 B2
• Filed: 08/19/2004
• Issued: 08/08/2006
• Est. Priority Date: 08/19/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Canaud, Thierry, Hartmann, Udo
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/922,005
• Publication Number:
  US 20050068055A1
• Time in Patent Office: 719 Days
• Field of Search: None
• US Class Current: 324/762.03
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Claims

1. A test system for testing semiconductor circuit chips comprising:

a primary test channel;

a plurality of parallel subchannels, each subchannel configured to have a first end coupled to the primary test channel and a second end configured to be coupled to an input of separate semiconductor chips under test; and

a buffering circuit arranged in each subchannel, wherein the buffering circuit comprises a field effect transistor and a pull-up resistor, the field effect transistor including a first electrode connected to a first end of the pull-up resistor and to the input of the separate semiconductor chip under test, and the pull-up resistor including a second end connected to at least one voltage source.

2. The test system of claim 1, wherein the buffering circuit comprises a depletion-type p-channel MOS field effect transistor.

3. The test system of claim 1, wherein the field effect transistor includes a gate electrode connected to the primary test channel and an electrode other than the first electrode and the gate electrode connected to ground.

4. The test system of claim 1, wherein the buffering circuit in each subchannel is the configured the same.

5. The test system of claim 1, comprising:

a driver amplifier coupled to the primary channel for receiving a test signal for the test system.

6. A test system for testing semiconductor circuit chips comprising:

a primary test channel;

a plurality of parallel subchannels, each subchannel configured to have a first end coupled to the primary test channel and a second end configured to be coupled to an input of separate semiconductor chips under test; and

a buffering circuit arranged in each subchannel, each buffering circuit including a field effect transistor and a pull-up resistor; and

a driver amplifier coupled to the primary channel for receiving a test signal for the test system, wherein a gate electrode of each field effect transistor is connected in common to the drive amplifier and a drain or source electrode of each field effect transistor is connected to one end of an associated pull-up resistor and the other end of the associated pull-up resistor is connected to at least one voltage source.

7. The test system of claim 6, wherein the field effect transistors are depletion-type p-channel MOS field effect transistors.

8. The test system of claim 6, comprising a voltage source coupled to the test system.

9. The test system of claim 6, comprising a selection of voltage sources coupled to the test system.

10. A test arrangement for testing semiconductor circuit chips, the test arrangement comprising:

a first test system comprising a first primary test channel, a plurality of parallel subchannels, each subchannel configured to have a first end coupled to the first primary test channel and a second end configured to be coupled to an input of a first set of separate semiconductor chips under test, a buffering circuit arranged in each subchannel, each buffering circuit including a field effect transistor and a pull-up resistor, and a first driver amplifier coupled to the first primary channel for receiving a first test signal, wherein a gate electrode of each field effect transistor is connected in common to the first drive amplifier; and

a second test system comprising a second primary test channel, a plurality of parallel sub channels, each subchannel configured to have a first end coupled to the second primary test channel and a second end configured to be coupled to an input of a second set of separate semiconductor chips under test, a buffering circuit arranged in each subchannel, each buffering circuit including a field effect transistor and a pull-up resistor, and a second driver amplifier coupled to the first primary channel for receiving a first test signal, wherein a gate electrode of each field effect transistor is connected in common to the second drive amplifier;

wherein one end of each of the pull-up resistors is connected to a freely selectable voltage source.

11. The test arrangement of claim 10, wherein a common voltage source is coupled to the first test system and the second test system.

12. The test system of claim 10, wherein a selection of voltage sources are coupled to the first test system and the second test system.

13. A test arrangement for testing semiconductor circuit chips comprising:

a primary test channel for receiving a test signal from a driver amplifier of an item of test equipment;

a plurality of parallel sub-channels for distributing the test signal to a plurality of inputs of one or more semiconductor circuit chips under test;

a signal buffering circuit arranged in each sub-channel to receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s), wherein all the signal buffering circuits have the same circuit arrangement and each includes a field effect transistor and a pull-up resistor, and where the drain or source electrode of each field effect transistor is connected to one end of the associated pull-up resistor and to the respective chip input via the associated sub-channel, the gate electrodes of the field effect transistors are connected in common to the driver amplifier, and the other electrodes of the drain and source electrodes of the field effect transistors that are not connected to the pull-up resistor are connected in common to ground, and the other ends of the pull-up resistors are connected to at least one voltage source.

14. The test arrangement of claim 13, wherein the at least one voltage source is an external voltage source, separate from the test equipment, that allows unrestricted selection of the voltages supplied by it.

15. The test arrangement of claim 14, wherein the inputs of the semiconductor circuit chips under test are functionally identical and exactly one voltage source is provided.

16. The test arrangement of claim 13, wherein the inputs of the semiconductor circuit chips under test are functionally identical and exactly one voltage source is provided.

17. The test arrangement of claim 13, wherein it is designed for one driver amplifier and has a plurality of buffering circuit groups which, supplied by a dedicated voltage source for each group, transmit to functionally non-identical inputs via the sub-channels test signals having different levels but the same signal form.

18. The test arrangement of claim 13, wherein it is designed for a plurality of driver amplifiers and a corresponding number of primary test channels, and has exactly one voltage source and a plurality of buffering circuit groups supplied by this, each of which is connected on the input side to one of the primary test channels, and transmits to functionally non-identical inputs test signals that have a different signal form for each group but the same level.

19. The test arrangement of claim 14, wherein it is designed for a plurality of driver amplifiers and a corresponding number of primary test channels, and has exactly one voltage source and a plurality of buffering circuit groups supplied by this, each of which is connected on the input side to one of the primary test channels, and transmits to functionally non-identical inputs test signals that have a different signal form for each group but the same level.

20. The test arrangement of claim 13, the field effect transistors are depletion-type p-channel MOS field effect transistors.