LVDS input circuit with extended common mode range

• US 7,088,166 B1
• Filed: 06/17/2004
• Issued: 08/08/2006
• Est. Priority Date: 06/19/2003
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Reinschmidt, Robert M., Krishnamurthy, Dilip
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/871,582
• Time in Patent Office: 782 Days
• Field of Search: None
• US Class Current: 327/333
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A low voltage differential signal (LVDS) input circuit with extended common mode range has been disclosed. One embodiment of the LVDS input circuit includes a first resistor coupled between a differential logic circuit and a first input pad, a second resistor coupled between the differential logic circuit and a second input pad, and a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node. Other embodiments are described and claimed.

Claims

1. An apparatus, comprising:

a first resistor coupled between a differential logic circuit and a first input pad;

a second resistor coupled between the differential logic circuit and a second input pad;

a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node;

a plurality of pull-up current mirrors coupled to the first and second resistors; and

a plurality of pull-down current mirrors coupled to the first and second resistors.

2. The apparatus of claim 1, further comprising:

a third resistor coupled between the plurality of pull-up current mirrors and the node; and

a fourth resistor coupled between the plurality of pull-down current mirrors and the node.

3. The apparatus of claim 1, wherein the plurality of pull-up current mirrors include a first, a second, and a third pull-up transistors, each of the first, second, and third pull-up transistors has a source, a gate, and a drain, the first, second, and third pull-up transistors are coupled to each other at the gates of the first, second, and third pull-up transistors, and the sources of the first, second, and third pull-up transistors are coupled to a power supply.

4. The apparatus of claim 3, wherein the power supply is at or above approximately 1.2V and a common mode range of a first and a second low voltage differential signal (LVDS) input signals at the first and second input pads, respectively, is from approximately 0.6V to approximately 2.4V.

5. The apparatus of claim 3, wherein the plurality of pull-down current mirrors includes a first, a second, and a third pull-down transistors, each of the first, second, and third pull-down transistors has a source, a gate, and a drain, the first, second, and third pull-down transistors are coupled to each other at the gates of the first, second, and third pull-down transistors, and the sources of the first, second, and third pull-up transistors are coupled to a ground.

6. The apparatus of claim 1, further comprising:

a network interface device including the differential logic circuit, the first and second resistors, and the first and second termination resistors; and

a plurality of signal lines coupled to the network interface device to propagate signals to the network interface.

7. The apparatus of claim 6, further comprising:

a switch including the network interface device; and

a router coupled to the plurality of signal lines to send the signals over the signal lines to the switch.

8. The apparatus of claim 6, further comprising:

a processor including the network interface device; and

a storage device coupled to the plurality of signal lines to send the signals over the signal lines to the processor.

9. A method, comprising:

translating a first and a second low voltage differential signal (LVDS) input signals into a first and a second differential input signals through a first and a second translation resistors, respectively, within a LVDS input circuit;

inputting the first and the second differential input signals to a differential logic circuit within the LVDS input circuit;

dividing a difference between the first and the second LVDS input signals over a first and a second termination resistors, which are coupled to each other in series, to produce a common mode reference voltage at a node between the first and the second termination resistors; and

setting currents through a plurality of pull-up current mirrors, a plurality of pull-down current mirrors, a first resistor, and a second resistor using the common mode reference voltage to cause a difference between the differential input signals to be substantially constant, wherein the first resistor is coupled between the node and the plurality of pull-up current mirrors and the second resistor is coupled between the node and the plurality of pull-down current mirrors.

10. The method of claim 9, further comprising:

extending a common mode range of the LVDS input circuit using the plurality of pull-up current mirrors, the plurality of pull-down current mirrors, and the first and second translation resistors.

11. The method of claim 9, further comprising amplifying a swing of the first and the second differential input signals using the differential logic circuit.

12. An apparatus, comprising:

means for extending an upper limit of a common mode range of a first and a second low voltage differential signal (LVDS) input signals beyond a power supply voltage provided to the LVDS input circuit; and

means for producing a first and a second substantially constant differential input signals from the first and the second LVDS input signals, wherein the means for producing a first and a second substantially constant differential input signals comprises a plurality of pull-up current mirrors and a plurality of pull-down current mirrors.

13. The apparatus of claim 12, wherein the power supply voltage is at or above approximately 1.2V and the common mode range of the first and the second LVDS input signals is from approximately 0.6V to approximately 2.4V.

14. The apparatus of claim 12, further comprising:

means for amplifying a swing of the first and the second differential input signals.

15. A method, comprising:

translating a pair of differential signals to modify a common mode voltage of the pair of differential signals such that the translated pair of differential signals is compatible with a differential Metal Oxide Semiconductor (MOS) amplifier;

inputting the translated pair of differential signals into the differential MOS amplifier; and

setting currents through a plurality of pull-up current mirrors and a plurality of pull-down current mirrors to cause a difference between the pair of differential signals to be substantially constant.

16. The method of claim 15, further comprising:

amplifying the translated pair of differential signals using the differential MOS amplifier.