Voltage-controlled oscillators having controlling circuits

• US 7,088,190 B2
• Filed: 05/28/2004
• Issued: 08/08/2006
• Est. Priority Date: 05/28/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Beacom, Melissa A., Masenas, Charles J., Austin, John S.
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US10/709,811
• Publication Number:
  US 20050275476A1
• Time in Patent Office: 802 Days
• Field of Search: 331/57, 327/149
• US Class Current: 331/57
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

Claims

1. An oscillator delay stage circuit operating between first and second operating voltages, wherein the first operating voltage is higher than the second operating voltage, the oscillator delay stage circuit comprising:

(a) an inverting circuit including an input node and an output node,

wherein the inverting circuit is configured to receive an input signal from the input node and generate an output signal to the output node, and

wherein the inverting circuit is further configured to increase the output signal in voltage in response to the input signal decreasing in voltage and to decrease the output signal in voltage in response to the input signal increasing in voltage; and

(b) a control circuit including (i) a first switch circuit and a first resistance adjusting circuit electrically coupled in series between the output node and the second operating voltage, and (ii) a second switch circuit and a second resistance adjusting circuit electrically coupled in series between the output node and the first operating voltage,

wherein in response to the input signal increasing in voltage towards the first operating voltage, the first switch circuit is configured to decrease in resistance,

wherein in response to the input signal decreasing in voltage towards the second operating voltage, the second switch circuit is configured to decrease in resistance,

wherein the first resistance adjusting circuit is configured to receive as input an external control signal and to change in resistance in response to a change of the external control signal,

wherein the second resistance adjusting circuit is configured to receive as input the external control signal and to change in resistance in response to a change of the external control signal, and

wherein the second resistance adjusting circuit comprises a first n-channel transistor.

2. The oscillator delay stage circuit of claim 1, wherein the first switch circuit comprises a second transistor having a gate terminal configured to receive the input signal,

wherein the first resistance adjusting circuit electrically couples the first switch circuit to the output node, and

wherein the second resistance adjusting circuit electrically couples the second switch circuit to the output node.

3. The oscillator delay stage circuit of claim 2, wherein the second transistor is an n-channel transistor.

4. The oscillator delay stage circuit of claim 1, wherein the first resistance adjusting circuit comprises a third transistor having a gate terminal configured to receive the external control signal.

5. The oscillator delay stage circuit of claim 4, wherein the third transistor is an n-channel transistor.

6. The oscillator delay stage circuit of claim 1, wherein the inverting circuit comprises a CMOS inverter.

7. The oscillator delay stage circuit of claim 1, wherein the control circuit further comprises an extrinsic capacitor electrically coupled between the output node and the second operating voltage.

8. An oscillator delay stage circuit operating between first and second operating voltages, wherein the first operating voltage is higher than the second operating voltage, the oscillator delay stage circuit comprising:

(a) an inverting circuit including an input node and an output node,

wherein the inverting circuit is configured to receive an input signal from the input node and generate an output signal to the output node, and

wherein the inverting circuit is further configured to increase the output signal in voltage in response to the input signal decreasing in voltage and to decrease the output signal in voltage in response to the input signal increasing in voltage; and

(b) a control circuit including a first switch circuit and a first resistance adjusting circuit electrically coupled in series between the output node and the first operating voltage,

wherein in response to the input signal decreasing in voltage towards the second operating voltage, the first switch circuit is configured to decrease in resistance,

wherein the first resistance adjusting circuit is configured to receive as input an external control signal and to change in resistance in response to a change of the external control signal,

wherein the first resistance adjusting circuit comprises a first n-channel transistor, and

wherein the first resistance adjusting circuit electrically couples the first switch circuit to the output node.

9. The oscillator delay stage circuit of claim 8, wherein the first switch circuit comprises a second transistor having a gate terminal configured to receive the input signal.

10. The oscillator delay stage circuit of claim 9, wherein the second transistor is a p-channel transistor.

11. The oscillator delay stage circuit of claim 8, wherein the first n-channel transistor comprises a gate terminal configured to receive the external control signal.

12. The oscillator delay stage circuit of claim 8, wherein the inverting circuit comprises a CMOS inverter.

13. The oscillator delay stage circuit of claim 8, wherein the control circuit further comprises an extrinsic capacitor electrically coupled between the output node and the first operating voltage.

14. A method for signal generation, the method comprising the steps of:

(a) providing a voltage-controlled oscillator comprising N oscillator delay stage circuits operating between first and second operating voltages, N being an odd integer, the first operating voltage being higher than the second operating voltage, wherein each of the N oscillator delay stage circuits comprises;

(i) an inverting circuit including an input node and an output node, and

(ii) a control circuit including a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and the first operating voltage,

wherein the resistance adjusting circuit comprises a first n-channel transistor;

(b) applying to the resistance adjusting circuit an external control signal so as to achieve a target operating frequency for the voltage-controlled oscillator;

(c) in response to an input signal decreasing in voltage at the input node,

(i) using the inverting circuit to increase an output signal in voltage at the output node, and

(ii) decreasing the resistance of the switch circuit.

15. The method of claim 14, wherein the switch circuit comprises a second transistor having a gate terminal configured to receive the input signal, wherein the resistance adjusting circuit electrically couples the switch circuit to the output node.

16. The method of claim 14, wherein the first n-channel transistor comprises a gate terminal configured to receive the external control signal.

17. The method of claim 14, wherein the inverting circuit comprises a CMOS inverter.