Distributed write data drivers for burst access memories

• US 7,088,625 B2
• Filed: 09/22/2004
• Issued: 08/08/2006
• Est. Priority Date: 12/23/1994
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/946,772
• Publication Number:
  US 20050036367A1
• Time in Patent Office: 685 Days
• Field of Search: 365/189.01, 365/189.05, 365/189.09, 365/230.06, 365/203, 365/236
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

Claims

1. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

2. The method of claim 1, wherein disabling the data driver enable circuits in response to asserting the equilibration signal comprises gating a version of the write enable signal with the equilibration signal.

3. The method of claim 1, wherein the recited steps are initiated in the recited order.

4. The method of claim 1, wherein providing the first address from a microprocessor to the burst access memory comprises inputting a single address to a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin.

5. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory organized according to a prefetch architecture and including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

6. The method of claim 5, wherein the write enable signal is an active-low signal.

7. A method of storing data in a system, comprising:

providing a burst access memory organized according to a pipelined architecture and including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

8. The method of claim 7, wherein the write enable signal is an active-low signal.

9. A method of storing data in a system, comprising:

providing a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

10. The method of claim 9, wherein providing the second data bit comprises providing a second plurality of data bits, latching the second plurality of data bits with a successive transition of the active-low column address strobe signal, the successive transition immediately succeeding the transition of the column address strobe signal used to latch the first plurality of data bits.

11. The method of claim 9, wherein the write enable signal is an active-low signal.

12. A method of storing data in a system, comprising:

providing a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to each transition of a column-address strobe signal;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

13. The method of claim 12, wherein the write enable signal is an active-low signal.

14. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to receiving a plurality of pulses of a column-address strobe signal;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

15. The method of claim 14, wherein the write enable signal is an active-low signal.