Distributed write data drivers for burst access memories
First Claim
1. A method of storing data in a system, comprising:
- providing a first address from a microprocessor to a burst access memory;
providing a first data bit to the memory;
asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;
storing the first data bit in a memory cell selected by the first address;
advancing an address counter within the memory to provide a second address;
providing a second data bit to the memory;
asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;
disabling the data driver enable circuits in response to asserting the equilibration signal;
deasserting the equilibration signal; and
storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.
1 Assignment
0 Petitions
Accused Products
Abstract
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
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Citations
15 Claims
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1. A method of storing data in a system, comprising:
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providing a first address from a microprocessor to a burst access memory; providing a first data bit to the memory; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (2, 3, 4)
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5. A method of storing data in a system, comprising:
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providing a first address from a microprocessor to a burst access memory organized according to a prefetch architecture and including; a memory array coupled to a column decoder and a row decoder, a latch coupled to the row decoder; an active-low row address strobe input coupled to the latch; a plurality of address inputs coupled to the latch; a counter coupled between the plurality of address inputs and the column decoder; and an active-low column address strobe input coupled to the counter; providing a first data bit to the memory; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (6)
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7. A method of storing data in a system, comprising:
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providing a burst access memory organized according to a pipelined architecture and including; a memory array coupled to a column decoder and a row decoder, a latch coupled to the row decoder; an active-low row address strobe input coupled to the latch; a plurality of address inputs coupled to the latch; a counter coupled between the plurality of address inputs and the column decoder; and an active-low column address strobe input coupled to the counter; providing a first address to the memory from a microprocessor; providing a first data bit to the memory; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (8)
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9. A method of storing data in a system, comprising:
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providing a burst access memory including; a memory array coupled to a column decoder and a row decoder, a latch coupled to the row decoder; an active-low row address strobe input coupled to the latch; a plurality of address inputs coupled to the latch; a counter coupled between the plurality of address inputs and the column decoder; and an active-low column address strobe input coupled to the counter; providing a first address to the memory from a microprocessor; providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (10, 11)
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12. A method of storing data in a system, comprising:
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providing a burst access memory including; a memory array coupled to a column decoder and a row decoder, a latch coupled to the row decoder; an active-low row address strobe input coupled to the latch; a plurality of address inputs coupled to the latch; a counter coupled between the plurality of address inputs and the column decoder; and an active-low column address strobe input coupled to the counter; providing a first address to the memory from a microprocessor; providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to each transition of a column-address strobe signal; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (13)
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14. A method of storing data in a system, comprising:
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providing a first address from a microprocessor to a burst access memory including; a memory array coupled to a column decoder and a row decoder, a latch coupled to the row decoder; an active-low row address strobe input coupled to the latch; a plurality of address inputs coupled to the latch; a counter coupled between the plurality of address inputs and the column decoder; and an active-low column address strobe input coupled to the counter; providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched; asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers; storing the first data bit in a memory cell selected by the first address; advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to receiving a plurality of pulses of a column-address strobe signal; providing a second data bit to the memory; asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits; disabling the data driver enable circuits in response to asserting the equilibration signal; deasserting the equilibration signal; and storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal. - View Dependent Claims (15)
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Specification