Column redundancy scheme for non-volatile flash memory using JTAG input protocol
First Claim
1. A serially-programmable integrated circuit (IC) comprising:
- a first input connector for receiving serial programming data;
a memory array having a first width, the memory array comprising a plurality of primary columns and a plurality of redundant columns, the plurality of primary columns having a second width and the plurality of redundant columns having a third width;
a data register coupled to receive the serial programming data from the first input connector, the data register comprising a shift register having a fourth width, the fourth width being a divisor of the second width and the third width;
a bitline latch for loading a data word into the memory array, the bitline latch having the first width; and
a column multiplexer for performing a loading operation to load data in parallel from the data register into the bitline latch.
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Accused Products
Abstract
A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the next portion is shifted into the data register. The programming bitstream portions fill the bitline latch sequentially unless a count indicator for a particular portion matches a predetermined defective column value, in which case that bitstream portion is rerouted to a region of the bitline latch associated with the redundant columns of the memory array. The count indicator is incremented with each new bitstream portion shifted into the data register. Once the programming bitstream is fully loaded into the bitline latch, the data is programmed into a selected row of the memory array in page mode.
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Citations
21 Claims
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1. A serially-programmable integrated circuit (IC) comprising:
a first input connector for receiving serial programming data; a memory array having a first width, the memory array comprising a plurality of primary columns and a plurality of redundant columns, the plurality of primary columns having a second width and the plurality of redundant columns having a third width; a data register coupled to receive the serial programming data from the first input connector, the data register comprising a shift register having a fourth width, the fourth width being a divisor of the second width and the third width; a bitline latch for loading a data word into the memory array, the bitline latch having the first width; and a column multiplexer for performing a loading operation to load data in parallel from the data register into the bitline latch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An integrated circuit (IC) comprising:
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a Test Access Port (TAP) port including a test data input (TDI) terminal; a memory array having a first width, the memory array including a plurality of primary columns and a plurality of redundant columns; a data register coupled to the TDI terminal, the data register having a second width, the second width being less than the first width; and a bitline latch coupled between the data register and the memory array, the bitline latch having the first width. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification