Time and frequency synchronization in multi-input, multi-output (MIMO) systems

• US 7,088,782 B2
• Filed: 04/24/2002
• Issued: 08/08/2006
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: American Patents LLC
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Stuber, Gordon L., Mody, Apurva N.
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US10/128,821
• Publication Number:
  US 20020181509A1
• Time in Patent Office: 1,567 Days
• Field of Search: 375/260, 375/299, 375/347, 375/267, 370/208, 370/210, 370/209
• US Class Current: 375/260
• CPC Class Codes: H04B 7/04 using two or more spaced independent antennas
• CPC Class Codes: H04L 1/0618 Space-time coding
• CPC Class Codes: H04L 27/2602 Signal structure
• CPC Class Codes: H04L 27/26035 Maintenance of orthogonality, e.g. for signals exchanged between cells or users, or by using covering codes or sequences using different training sequence per antenna H04B7/0684; code allocation H04J13/16

Abstract

In a communication system, and in particular a wireless Orthogonal Frequency Division Multiplexing (OFDM) communication system, the present invention provides systems for synchronizing data transmitted across a channel. The present invention may be used in a Multi-Input, Multi-Output (MIMO) system in which the data is transmitted from any number of transmitting antennas and received by any number of receiving antennas. The number of transmitting and receiving antennas does not necessarily have to be the same. Circuitry is provided for synchronizing the data in both the time domain and frequency domain. Time synchronization involves coarse time synchronization and fine time synchronization. Frequency synchronization involves coarse frequency offset estimation, fine frequency offset estimation, and frequency offset correction.

Claims

1. An apparatus for synchronizing a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system, the apparatus comprising:

a number (Q) of OFDM modulators, each OFDM modulator producing a frame comprising at least one inserted symbol, a plurality of data symbols, and cyclic prefixes;

Q transmitting antennas, each transmitting antenna connected to a respective OFDM modulator, for transmitting said frame over a channel;

a number (L) of receiving antennas for receiving the transmitted frames; and

L OFDM demodulators, each OFDM demodulator corresponding to a respective receiving antenna, the L OFDM demodulators comprising a synchronization circuit, which processes the received frame in order to synchronize the received frame in a time domain and frequency domain;

wherein the synchronization circuit comprises a first portion that includes individual circuits such that each individual circuit is used exclusively by a respective OFDM demodulator, and a second portion that includes circuits that are shared by all of the L OFDM demodulators.

2. The apparatus of claim 1, wherein the cyclic prefixes protect the data symbols against Inter Symbol Interference (ISI).

3. The apparatus of claim 1, wherein the at least one inserted symbol has at least one pilot symbol inserted within the data symbols or at least one training symbol inserted at the beginning of the frame.

4. The apparatus of claim 1, wherein the synchronization circuit comprises a circuit for finding the optimum time instant of the start of the demodulated frame.

5. The apparatus of claim 4, wherein the synchronization circuit comprises a coarse time synchronization circuit and a fine time synchronization circuit.

6. The apparatus of claim 5, wherein the coarse time synchronization circuit comprises a circuit for performing auto-correlation on the received frame over a particular window.

7. The apparatus of claim 5, wherein the coarse time synchronization circuit comprises a circuit for performing an automatic gain control operation.

8. The apparatus of claim 1, wherein each of the Q OFDM modulators comprises a transmitting local oscillator, each of the L OFDM demodulators comprises a receiving local oscillator, and the synchronization circuit comprises a first frequency offset estimation circuit and a second frequency offset estimation circuit for estimating the frequency difference between the transmitting local oscillator and the receiving local oscillator.

9. The apparatus of claim 8, wherein the second frequency offset estimation circuit is used to correct the frequency of the receiving local oscillator.

10. The apparatus of claim 8, wherein said synchronization circuit further comprises a frequency offset correction circuit that utilizes the estimates from said second frequency offset estimation circuit and said first frequency offset estimation circuit to correct the frequency offset in discrete time.

11. The apparatus of claim 1, wherein each of the Q OFDM modulators share a common transmitting local oscillator, each of the L OFDM demodulators share a common receiving local oscillator, and the synchronization circuit comprises first and second frequency offset estimation circuits for estimating the frequency difference between the transmitting local oscillator and the receiving local oscillator.

12. The apparatus of claim 1, wherein Q is equal to L.

13. The apparatus of claim 12, wherein Q is equal to one.

14. The apparatus of claim 1, wherein Q equals two.

15. The apparatus of claim 1, wherein Q is not equal to L.

16. The apparatus of claim 1 further comprising an OFDM encoder, wherein the OFDM encoder comprises:

a channel encoder;

a symbol mapper connected to an output of the channel encoder;

a space-time processor connected to an output of the symbol mapper, the space-time processor separating data into a plurality of sub-channels; and

a pilot/training symbol inserter, which inserts pilot symbols and training symbols onto the sub-channels.

17. The apparatus of claim 1, wherein each of the Q OFDM modulators comprises:

a serial-to-parallel converter;

an inverse discrete Fourier transform (IDFT) stage connected to an output of the serial-to-parallel converter;

a cyclic prefix inserter connected to an output of the IDFT stage;

a parallel-to-serial converter connected to an output of the cyclic prefix inserter;

a digital-to-analog converter (DAC) connected to an output of the parallel-to-serial converter;

a local oscillator;

a mixer having a first input and a second input, the first input connected to an output of the DAC, the second input connected to an output of the local oscillator; and

an amplifier connected to an output of the mixer.

18. The apparatus of claim 1, wherein each of the L OFDM demodulators comprises:

a pre-amplifier;

a local oscillator;

a mixer having a first input and a second input, the first input connected to an output of the pre-amplifier, the second input connected to an output of the local oscillator;

an analog-to-digital converter (ADC) connected to an output of the mixer;

the synchronization circuit, having one input connected to an output of the ADC;

a cyclic prefix remover connected to an output of the synchronization circuit;

a serial-to-parallel converter connected to an output of the cyclic prefix remover; and

a discrete Fourier transform (DFT) stage connected to an output of the serial-to-parallel converter, an output of the DFT stage connected to another input to the synchronization circuit.

19. The apparatus of claim 1, wherein the L OFDM demodulators share a single synchronization circuit.

20. The apparatus of claim 1, wherein each OFDM demodulator uses one of L synchronization circuits.

21. The apparatus of claim 1, wherein the second portion comprises a first frequency offset estimator circuit and a second frequency offset estimator circuit, and the first portion comprises a coarse time synchronization circuit, a fine time synchronization circuit, and a frequency offset correction circuit.

22. The apparatus of claim 1, wherein the second portion comprises a coarse time synchronization circuit, a first frequency offset estimator circuit, and a second frequency offset estimator circuit, and the first portion comprises a fine time synchronization circuit and a frequency offset correction circuit.

23. The apparatus of claim 1, wherein the first portion comprises coarse time synchronization circuits wherein the results of the different coarse time synchronization circuits are shared by the different OFDM demodulators.

24. The apparatus of claim 1 further comprising an OFDM decoder, wherein the OFDM decoder comprises:

a space-time processor that receives an output from each of the L OFDM demodulators;

a parameter estimator that receives an output from each of the L OFDM demodulators and estimates parameters of the channel;

a parallel-to-serial converter connected to an output of the space-time processor;

a symbol demapper having a first input and second input, the first input connected to an output of the parameter estimator, the second input connected to an output of the parallel-to-serial converter; and

a channel decoder connected to an output of the symbol demapper.

25. A synchronization circuit, incorporated within a demodulator of a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system, wherein the synchronization circuit comprises:

a coarse time synchronization circuit;

a first frequency offset estimation circuit connected to a first output of the coarse time synchronization circuit;

a second frequency offset estimation circuit connected to a first output of the first frequency offset estimation circuit;

a fine time synchronization circuit having a first input connected to a first output of the second frequency offset estimation circuit; and

a frequency offset correction circuit having inputs connected to second outputs of the coarse time synchronization circuit, first frequency offset estimation circuit, and second frequency offset estimation circuit, and having an output connected to a second input to the fine time synchronization circuit.

26. The apparatus of claim 25, wherein the coarse time synchronization circuit is an auto-correlation circuit that comprises:

a delay circuit that receives a stream of data samples of a received frame;

a complex conjugation circuit connected to an output of the delay circuit;

a mixer having a first input and a second input, the first input receiving the stream of data samples, the second input connected to an output of the complex conjugation circuit; and

a summing circuit connected to an output of the mixer.

27. The apparatus of claim 25, wherein the first frequency offset estimation circuit comprises an offset correction circuit.

28. The apparatus of claim 25, wherein the second frequency offset estimation circuit is a cross-correlation circuit in a frequency domain that comprises:

a first buffer that receives and stores a portion of a stream of data samples from a Discrete Fourier Transform (DFT) stage, the first buffer having a plurality of outputs;

a second buffer that receives and stores a portion of a stream of data samples in the frequency domain from a transmitted sequence, the second buffer having a plurality of outputs;

a plurality of complex conjugation circuits connected to the plurality of outputs of the second buffer;

a plurality of mixers, each mixer having a first input and a second input, the first inputs connected to the outputs of the first buffer, the second inputs connected to outputs of the complex conjugation circuits; and

a summing circuit that sums the outputs of the mixers.

29. The apparatus of claim 25, wherein the fine time synchronization circuit is a cross-correlating pattern recognition circuit that comprises:

a first buffer that receives and stores a portion of a stream of data samples of a received frame, the first buffer having a plurality of outputs;

a second buffer that receives and stores a portion of a transmitted sequence in a time domain, the second buffer having a plurality of outputs;

a plurality of complex conjugation circuits connected to the plurality of outputs of the second buffer;

a plurality of mixers, each mixer having a first input and a second input, the first inputs connected to the outputs of the first buffer, the second inputs connected to outputs of the complex conjugation circuits; and

a summing circuit that sums the outputs of the mixers.

30. A method for synchronizing a Multi-Input Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system in time and frequency domains, the method comprising the steps of:

producing a frame of data comprising a training symbol that includes a synchronization component that aids in synchronization, a plurality of data symbols, and a plurality of cyclic prefixes;

transmitting the frame over a channel;

receiving the transmitted frame;

demodulating the received frame;

synchronizing the received demodulated frame to the transmitted frame such that the data symbols are synchronized in the time domain and frequency domain;

wherein the synchronizing in the time domain comprises coarse time synchronizing and fine time synchronizing.

31. The method of claim 30, wherein the synchronizing in the time domain includes averaging estimates over a period of time.

32. The method of claim 30, wherein the synchronizing in the frequency domain comprises estimating a frequency offset.

33. The method of claim 32, wherein the step of estimating the frequency offset comprises estimating the frequency offset to within one half of the sub-carrier spacing.

34. The method of claim 33, wherein the step of estimating the frequency offset further comprises the steps of:

repeating received samples of the received frame a number of times;

taking an N-point Fast Fourier Transform (FFT); and

performing a cross-correlation procedure in the frequency domain.

35. The method of claim 32, wherein the step of estimating the frequency offset comprises averaging the estimates over a number of frames, thereby improving the estimates.

36. The method of claim 32, wherein the step of estimating the frequency offset comprises taking the estimates from a number of different OFDM demodulators and averaging the estimates, thereby improving the estimates.

37. The method of claim 30, wherein the transmitting step includes transmitting the symbols from at least two antennas.

38. The method of claim 30, wherein the step of producing further comprises producing said training symbol with an orthogonal sequence, thereby enhancing a fine time synchronization performance.

39. The method of claim 30, wherein the step of producing further comprises adjusting the periodicity of the training symbol, thereby increasing the range of frequency offset estimation.

40. The method of claim 30, wherein the synchronization component aids in synchronization and in an estimation of channel parameters.

41. The method of claim 30, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols less than a number of transmitting antennas.

42. The method of claim 30, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols equal to a number of transmitting antennas.

43. The method of claim 30, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols greater than a number of transmitting antennas.

44. The method of claim 30, wherein the synchronization component comprises a preamble whose signal transmission matrix resembles an existing space-time block code.

45. The method of claim 30, wherein the synchronization component includes chirp-like sequences.

46. The method of claim 45, wherein the chirp-like sequences include at least one of Frank-Zadoff sequences, Chu sequences, Milewski sequences, Suehiro polyphase sequences, and Ng et al. sequences.

47. The method of claim 30, wherein the step of producing a frame comprises producing the cyclic prefixes in a preamble and in the data symbols such that the cyclic prefixes in the preamble are longer than the cyclic prefixes in the data symbols, thereby countering an extended channel impulse response and improving synchronization.

48. The method of claim 30, further comprising the step of altering the training symbol to enhance the synchronization performance.

49. The method in claim 30, wherein the coarse time synchronizing includes averaging the coarse time synchronized results over time.

50. The method of claim 30, further comprising the steps of:

generating an N-point representation of the transmitted sequence in the frequency domain;

repeating the time domain sequence a number of times; and

taking an N-point Fast Fourier Transform.

51. The method of claim 30, wherein the step of producing comprises producing a preamble whose signal transmission matrix resembles an existing space-time block code.