Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus
First Claim
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1. A signal processing circuit comprising:
- an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means,wherein said arithmetic processing circuit comprisesa plurality of switch block means each including a plurality of switch elements and a plurality of signal lines,analog processing block means for executing predetermined signal modulation for an input signal, anda signal line for connecting said switch block means or said analog processing block means, andsaid circuit arrangement control means controls an ON/OFF pattern of operations of the plurality of switch elements or a signal modulation amount at said analog processing block means, thereby reconfiguring said arithmetic processing circuit to execute a plurality of different signal processing functions.
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Abstract
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.
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Citations
38 Claims
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1. A signal processing circuit comprising:
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an arithmetic processing circuit; circuit arrangement information storage means for storing circuit arrangement information; and circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit comprises a plurality of switch block means each including a plurality of switch elements and a plurality of signal lines, analog processing block means for executing predetermined signal modulation for an input signal, and a signal line for connecting said switch block means or said analog processing block means, and said circuit arrangement control means controls an ON/OFF pattern of operations of the plurality of switch elements or a signal modulation amount at said analog processing block means, thereby reconfiguring said arithmetic processing circuit to execute a plurality of different signal processing functions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A signal processing circuit comprising:
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an arithmetic processing circuit; circuit arrangement information storage means for storing circuit arrangement information; and circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal, said arithmetic processing circuit comprises a plurality of arithmetic processing blocks, each of said arithmetic processing blocks comprises an adaptive processing block capable of changing a processing function including signal modulation for the input signal on the basis of a control signal contained in the arrangement control signal, and a plurality of switch blocks arranged between signal lines for connecting said adaptive processing block and another arithmetic processing block to connect/disconnect the signal lines on the basis of the control signal contained in the arrangement control signal, and said arithmetic processing circuit realizes the different signal processing functions by controlling said switch blocks and said adaptive processing blocks in accordance with the arrangement control signal from said arrangement control means. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A pattern recognition apparatus comprising:
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time-division data input means for time serially inputting pattern data having a predetermined size as part of input data a plurality of number of times; position information input means for inputting position information of the pattern data on the input data; feature detection means, having a processing circuit, for detecting predetermined medium or higher order features related to a predetermined category from the pattern data; time serial integration processing means for time serially integrating outputs from said feature detection means on the basis of the position information and the feature category to generate feature detection map information; and determination means for outputting position information of the higher order feature in the input data and the category information on the basis of an output from said time serial integration processing means, wherein said processing circuit comprises; an arithmetic processing circuit; circuit arrangement information storage means for storing circuit arrangement information; and circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, and said arithmetic processing circuit executes a plurality of different signal processing functions by reconfiguring a circuit on the basis of the predetermined arrangement control signal. - View Dependent Claims (37, 38)
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Specification