Sharing of functions between an embedded controller and a host processor

• US 7,089,339 B2
• Filed: 03/16/2001
• Issued: 08/08/2006
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Falik, Ohad, Kirschner, Yuval, Friedman, Yehezkel, Flachs, Victor
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): Huynh, Kim T.
• Application Number:
  US09/810,746
• Publication Number:
  US 20020133655A1
• Time in Patent Office: 1,971 Days
• Field of Search: 710/240, 710/300, 710107-108, 710/200, 718/102, 714 1- 57
• US Class Current: 710/200
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

Claims

1. A system for allowing shared access by at least two processors including an embedded controller and a host processor to at least two modules, comprising:

a transaction control, wherein the embedded controller is capable of providing an indication of which of the modules to access to the transaction control, and wherein the host processor is capable of providing an indication of which of the modules to access to the transaction control; and

at least one access block bit controlled by one of the processors for blocking access by another of the processors to at least one of the modules, wherein the at least one access block bit is capable of enabling at least one of the modules, wherein enabling would activate said at least one of the modules.

2. The system of claim 1, further comprising a bus extension;

wherein at least one of the modules is accessible via said bus extension;

wherein said transaction control is capable of providing to said bus extension an indication of said at least one of the modules, accessible via said bus extension, for access by the host processor;

wherein said transaction control is capable of providing to said bus extension an indication of said at least one of the modules, accessible via said bus extension, for access by the embedded controller; and

wherein said bus extension is capable of providing an indication of said at least one of the modules for access by one of the processors.

3. The system of claim 1, wherein said transaction control is capable of providing an indication of at least one of the modules for access by one of the processors.

4. The system of claim 1, wherein at least one of the modules is part of an input/output chip.

16. The system of claim 2, wherein at least one of the modules comprises a memory accessible through the bus extension.

18. The system of claim 1, wherein the transaction control is further capable of allowing concurrent access by the processors to at least one of:

one or more of the modules, and one or more sub-modules within at least one of the modules.

19. The system of claim 1, further comprising:

at least one disable bit controlled by one of the processors, wherein the at least one disable bit is capable of disabling at least one of the modules even if the at least one access block bit is set to enable the at least one module; and

at least one tri-state bit controlled by one of the processors, wherein the at least one tri-state bit is capable of disabling an output of at least one of the modules even if the at least one access block bit is set to enable the at least one module.

20. The system of claim 1, wherein the at least one access block bit is capable of enabling at least one of the modules by activating the at least one module.

5. A method for allowing shared access to at least two modules by at least two processors including an embedded controller and a host processor, comprising the steps of:

receiving an indication from each of the processors of a module from among the at least two modules to access;

arbitrating between the processors in favor of one of the processors, wherein arbitrating between the processors comprises allowing one of the processors to control at least one access block bit, the at least one access block bit capable of blocking access by another of the processors to at least one of the modules, the at least one access block bit capable of enabling at least one of modules, wherein enabling would activate said at least one of the modules.

6. The method of claim 5, further comprising the step of:

blocking access by another of the processors to said module indicated by said one of the processors.

7. The method of claim 5, wherein said indication from each of the processors is for a different module to access.

17. The method of claim 5, wherein at least one of the modules comprises a memory accessible through a bus extension.

8. A method for allowing a processor comprising an embedded controller to access at least two modules affiliated with a device, comprising the steps of:

indicating the device;

indicating an access direction(read/write);

indicating one of the modules for accessing;

indicating a location for accessing, within said indicated one of the modules;

transferring data between said indicated location and the embedded controller; and

setting at least one access block bit to block access by another processor to at least one of the modules, wherein the at least one access block bit is capable of enabling at least one of the modules, wherein enabling would activate said at least one of the modules.

9. The method of claim 8, wherein said indicated one of the modules is accessible via a bus extension.

10. The method of claim 9, wherein said step of indicating one of the modules for accessing includes the step of:

indicating one of at least one chip select corresponding to said bus extension for accessing.

11. The method of claim 8, wherein said indicated one of the modules is part of an input/output chip.

12. The method of claim 11, wherein said step of indicating one of the modules for accessing includes the step of:

indicating a logical device number.

13. The method of claim 8, wherein said step of indicating a location for accessing includes the step of providing an indication of a location for accessing via an internal bus to said indicated one of said modules, the method further comprising the step of:

waiting for a freeing up of said internal bus before transferring said indication of a location for accessing onto said internal bus.

14. The method of claim 13, wherein said internal bus is occupied by a transaction originating from the other processor prior to said freeing up.

15. The method of claim 8, further comprising the step of:

the embedded controller waiting for receipt of data from said indicated location prior to initiating a subsequent access.