Managing accesses in a processor for isolated execution
First Claim
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1. A method comprising:
- setting a first processor in a processing system to operate in an isolated execution mode, wherein the first processor supports (a) the isolated execution mode in a ring 0 operating mode, (b) a normal execution mode in the ring 0 operating mode, and (c) one or more higher ring operating modes;
configuring the processing system to establish an isolated memory area in a memory of the processing system;
detecting, at the first processor, a snoop transaction from a second processor; and
disallowing the snoop transaction if (a) the snoop transaction requests access to an address that is cached by the first processor, (b) said address resides in the isolated memory area, and (c) the second processor is not set to operate in the isolated execution mode.
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Abstract
In one embodiment, a method comprises configuring an access transaction generated by a processor by a configuration storage containing configuration parameters. The processor has a normal execution mode and an isolated execution mode. The access transaction has access information. In a further embodiment, a method comprises checking the access transaction by an access checking circuit using at least one of the configuration parameters and the access information.
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Citations
22 Claims
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1. A method comprising:
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setting a first processor in a processing system to operate in an isolated execution mode, wherein the first processor supports (a) the isolated execution mode in a ring 0 operating mode, (b) a normal execution mode in the ring 0 operating mode, and (c) one or more higher ring operating modes; configuring the processing system to establish an isolated memory area in a memory of the processing system; detecting, at the first processor, a snoop transaction from a second processor; and disallowing the snoop transaction if (a) the snoop transaction requests access to an address that is cached by the first processor, (b) said address resides in the isolated memory area, and (c) the second processor is not set to operate in the isolated execution mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus for use in a processing system having memory, the apparatus comprising:
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a first processor for a processing system, wherein the first processor supports (a) an isolated execution mode in a ring 0 operating mode, (b) a normal execution mode in the ring 0 operating mode, and (c) one or more higher ring operating modes, the processor operable to detect a snoop transaction from a second processor; and an access checking circuit in the first processor, the access checking circuit operable to disallow the snoop transaction if (a) the snoop transaction requests access to an address that is cached by the first processor, (b) said address resides in an isolated memory area in a memory of the processing system, and (c) the second processor is not set to operate in the isolated execution mode. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A processing system comprising:
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first and second processors that can each be set to operate in a normal execution mode in a ring 0 operating mode and, alternatively, to operate in an isolated execution mode in the ring 0 operating mode, wherein the first processor also supports one or more higher ring operating modes, the first processor operable to detect a snoop transaction from the second processor; memory to include an isolated memory area, the memory responsive to the first processor; and an access checking circuit in the first processor, the access checking circuit operable to disallow the snoop transaction if (a) the snoop transaction requests access to an address that is cached by the first processor, (b) said address resides in the isolated memory area, and (c) the second processor is not set to operate in the isolated execution mode. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification