Method and system for performing placement on non Manhattan semiconductor integrated circuits

• US 7,089,519 B1
• Filed: 12/31/2002
• Issued: 08/08/2006
• Est. Priority Date: 12/31/2002
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven
• Primary Examiner(s): Thompson, A. M.
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/335,055
• Time in Patent Office: 1,316 Days
• Field of Search: 716/1, 716/2, 716 5- 8, 716 10- 13, 716/16, 716/17, 716/19, 257/785
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.

Claims

1. A method of designing an integrated circuit (“

IC”

) layout, said method comprising;

processing the IC layout with a Manhattan based placement program to produce an initial placement of the IC layout;

processing said initial placement with a non Manhattan based post processor to produce a non Manhattan based placement of the IC layout, wherein the processing of the initial placement is performed before a non Manhattan based routing; and

performing the non Manhattan based routing after processing the initial placement with the non Manhattan based post processor, wherein the non Manhattan based routing defines routes for a plurality of nets of the IC layout that did not have defined routes after the processing by the non Manhattan based post processor of the initial placement.

2. The method as claimed in claim 1, said method further comprising:

reducing a die size for said initial placement.

3. The method as claimed in claim 1, wherein said non Manhattan based post processor considers a timing placement metric.

4. The method as claimed in claim 3 wherein said non Manhattan based post processor considers non Manhattan wiring lengths.

5. The method as claimed in claim 1, said method further comprising:

processing a logical design with a Manhattan based placement program to create an initial die size; and

reducing said initial die size.

6. The method as claimed in claim 1, wherein said non Manhattan based post processor considers non Manhattan wiring lengths.

7. The method as claimed in claim 1, wherein said non Manhattan based post processor considers non Manhattan congestion.

8. The method as claimed in claim 6, wherein said non Manhattan based post processor considers non Manhattan congestion.

9. The method as claimed in claim 1, wherein said non Manhattan based post processor considers swaps and moves of circuit modules.

10. A computer readable medium, said computer readable medium comprising a set of computer instructions for an integrated circuit (“

IC”

) layout, said computer instructions implementing the steps of;

processing the IC layout with a Manhattan based placement program to produce an initial placement of the IC layout;

processing said initial placement with a non Manhattan based post processor to produce a non Manhattan based placement of the IC layout, wherein the processing of the initial placement is performed before a non Manhattan based routing; and

performing the non Manhattan based routing after processing the initial placement with the non Manhattan based post processor, wherein the non Manhattan based routing defines routes for a plurality of nets of the IC layout that did not have defined routes after the processing by the non Manhattan based post processor of the initial placement.

11. The computer readable medium as claimed in claim 10, said computer instructions further implementing:

reducing a die size for said initial placement.

12. The computer readable medium as claimed in claim 10, wherein said non Manhattan based post processor considers a timing placement metric.

13. The computer readable medium as claimed in claim 12, wherein said non Manhattan based post processor considers non Manhattan wiring lengths.

14. The computer readable medium as claimed in claim 10, said computer instructions further implementing:

processing a logical design with a Manhattan based placement program to create an initial die size; and

reducing said initial die size.

15. The computer readable medium as claimed in claim 10, wherein said non Manhattan based post processor considers non Manhattan wiring lengths.

16. The computer readable medium as claimed in claim 10, wherein said non Manhattan based post processor considers non Manhattan congestion.

17. The computer readable medium as claimed in claim 15, wherein said non Manhattan based post processor considers non Manhattan congestion.

18. The computer readable medium as claimed in claim 10, wherein said non Manhattan based post processor considers swaps and moves of circuit modules.