Dual strain-state SiGe layers for microelectronics
First Claim
1. A method for creating a strained crystalline layer having a tensilely strained SiGe layer portion and a compressively strained SiGe layer portion, comprising the step of:
- bonding epitaxially said strained crystalline layer over a SiGe relaxed buffer layer, wherein said tensilely strained SiGe and said compressively strained SiGe are epitaxially bonded over said SiGe relaxed buffer layer in coplanar spatial relation, wherein the Ge concentration of said tensilely strained SiGe is chosen to be below the Ge concentration of said SiGe relaxed buffer, and the Ge concentration of said compressively strained SiGe is chosen to be above the Ge concentration of said SiGe relaxed buffer.
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Abstract
A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.
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Citations
33 Claims
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1. A method for creating a strained crystalline layer having a tensilely strained SiGe layer portion and a compressively strained SiGe layer portion, comprising the step of:
bonding epitaxially said strained crystalline layer over a SiGe relaxed buffer layer, wherein said tensilely strained SiGe and said compressively strained SiGe are epitaxially bonded over said SiGe relaxed buffer layer in coplanar spatial relation, wherein the Ge concentration of said tensilely strained SiGe is chosen to be below the Ge concentration of said SiGe relaxed buffer, and the Ge concentration of said compressively strained SiGe is chosen to be above the Ge concentration of said SiGe relaxed buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method for creating a strained crystalline layer divided into two complementary regions, a first region consisting essentially of a tensilely strained SiGe layer, and a second region consisting essentially of a compressively strained SiGe layer, comprising the steps of:
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fabricating said tensilely strained SiGe layer; fabricating said compressively strained SiGe layer, wherein said compressively strained SiGe layer having essentially same thickness as said tensilely strained SiGe layer; removing said tensilely strained SiGe in places corresponding to said second region; removing said compressively strained SiGe layer in places corresponding to said first region; and bonding said tensilely strained SiGe layer and said compressively strained SiGe layer while interlocking said complementary first and second regions, whereby said tensilely strained SiGe layer and said compressively strained SiGe layer forming said strained crystalline layer divided into two complementary regions, and removing an excess of material covering said strained crystalline layer, whereby said excess of material resulted due to said bonding step. - View Dependent Claims (31)
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32. A method for fabricating a processor, comprising the step of:
using at least one chip, wherein said at least one chip is selected to comprise a strained crystalline layer having a tensilely strained SiGe layer portion and a compressively strained SiGe layer portion, wherein creating said crystalline layer comprise the step of bonding epitaxially said strained crystalline layer over a SiGe relaxed buffer layer, wherein said tensilely strained SiGe and said compressively strained SiGe are epitaxially bonded over said SiGe relaxed buffer layer in coplanar spatial relation, wherein the Ge concentration of said tensilely strained SiGe is chosen to be below the Ge concentration of said SiGe relaxed buffer, and the Ge concentration of said compressively strained SiGe is chosen to be above the Ge concentration of said SiGe relaxed buffer, and wherein a plurality of devices are hosted in said strained crystalline layer, and wherein said plurality of devices are chosen to comprise electron conduction type devices in said tensilely strained SiGe portion, and wherein said plurality of devices are chosen to comprise hole conduction type devices in said compressively strained SiGe portion. - View Dependent Claims (33)
Specification