Apparatus and method for pixel binning in an image sensor

• US 7,091,466 B2
• Filed: 12/19/2003
• Issued: 08/15/2006
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Bock, Nikolai E.
• Primary Examiner(s): Le, Que T.
• Application Number:
  US10/739,012
• Publication Number:
  US 20050133687A1
• Time in Patent Office: 970 Days
• Field of Search: 250/208.1
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned simultaneously. Pixels in an element are located in a plurality of rows and columns. In exemplary embodiments, pixel voltage signals or pixel current signals are binned.

Claims

1. A column circuit comprising:

n column lines, each column line being switchably connected to at least two pixels in a respective column via respective in-pixel row select switches and configured to receive pixel signals corresponding to incident light from the at least two pixels, where n is greater than or equal to 2; and

binning circuitry comprising n−

1 switches each switchably connecting two column lines to one another to bin pixel signals from the n column lines.

2. The column circuit of claim 1, wherein the n−

1 switches are transistors.

3. The column circuit of claim 1, wherein n equals 2.

4. The column circuit of claim 1, wherein n equals 4.

5. The column circuit of claim 1, wherein n equals 8.

20. The column circuit of claim 1, wherein each of the n−

1 switches switchably connects two adjacent column lines to one another.

6. A column circuit comprising:

n lines for receiving pixel current signals output from at least one pixel and corresponding to light incident on the at least one pixel, each line being connected to respective source follower transistor source/drain regions of at least two pixels in a respective column, the source follower transistors being of a first conductivity type where n is equal to or greater than 2; and

a plurality of current binning circuits to simultaneously bin pixel current signals from the pixels, each current binning circuit comprising a transistor of a second conductivity type, a gate and a source/drain region of the second conductivity type transistor connected to two of the lines.

7. The column circuit of claim 6, wherein n equals 2.

8. The column circuit of claim 6, wherein n equals 4.

9. The column circuit of claim 6, wherein n equals 8.

10. The pixel column circuit of claim 6, further comprising:

n column lines, each column line switchably connected to a ground potential, and wherein the gate and the source/drain region of the second conductivity type transistor are switchably connected to a predetermined voltage supply.

19. The column circuit of claim 6, further comprising (n/2)−

1 bin switches, each bin switch connecting two binning circuits to one another.

11. An image sensor comprising:

an array of pixels, the array comprising at least one pixel element, the at least one pixel element comprising a plurality of pixels in a plurality of columns and a plurality of rows, wherein the pixel element comprises pixels in n number of columns, where n is equal to or greater than 2, each pixel comprising a row select switch and configured to output a pixel signal representing light incident on the respective pixel;

a plurality of first column lines, each first column line being switchably connected to at least one pixel of a column of the element by a respective row select switch; and

binning circuitry connected to the plurality of first column output lines and configured to simultaneously bin pixel signals from pixels in at least two columns of the element, wherein the binning circuitry comprises n−

1 switches each for switchably connecting two column lines to one another.

12. The image sensor of claim 11, wherein the at least one pixel element comprises pixels located in a plurality of adjacent columns and a plurality of adjacent rows.

13. A processor system comprising:

a processor; and

an image sensor coupled to the processor, the image sensor comprising;

an array of pixels, the array comprising a plurality of pixel elements, at least one pixel element comprising a plurality of pixels in a plurality of columns and a plurality of rows, each pixel comprising a row select switch and configured to output a pixel signal representing light incident on the respective pixel and a source follower transistor of a first conductivity type and having a first source/drain region connected to the row select switch;

a plurality of first column lines, each first column line being switchably connected to at least one pixel of a column of the element by a respective row select switch; and

binning circuitry connected to the plurality of first column output lines and configured to simultaneously bin pixel signals from pixels in at least two columns of the element, wherein the binning circuitry comprises at least one current binning circuit, each current binning circuit comprising a transistor of a second conductivity type, a gate and a source/drain region of the second conductivity type transistor being connected to respective second source/drain regions of pixel source follower transistors of at least one pixel of at least two columns of the element.

21. The image sensor of claim 13, wherein the pixel element comprises pixels in n number of columns, where n is equal to or greater than 4 and an even number, wherein the binning circuitry comprises n/2 current binning circuits for binning pixel current signals and n/2−

1 switches switchably connecting the current binning circuits to one another.

14. A method of operating an image sensor, the image sensor comprising a plurality of pixels, the method comprising:

providing at least one pixel element, the at least one element comprising pixels in at least two rows and at least two columns, each pixel comprising a source follower transistor of a first conductivity type having a first source/drain region connected to a respective one of a plurality of first column lines and a second source/drain region connected to a row select switch, the row select switch for switchably connecting the second source/drain region to a respective one of a plurality of second column lines;

providing at least one binning circuit comprising a transistor of a first conductivity type having a gate and a first source/drain region connected to at least two first column lines; and

operating the image sensor in a binning mode by;

simultaneously binning pixel current signals from the at least one pixel element by selecting at least one row of pixels for readout, connecting the binning circuit to current readout circuitry and connecting the plurality of second column lines to a ground potential; and

reading out the binned pixel current signals.

15. The method of claim 14, wherein the act of operating the image sensor in a binning mode comprises simultaneously selecting pixels in all rows of the at least one pixel element for readout.

16. The method of claim 14, further comprising operating the image sensor in a non-binning mode by reading out individual pixel voltage signals.

17. The method of claim 16, further comprising changing between the binning mode and the non-binning mode.

18. The method of claim 16, wherein operating the image sensor in a non-binning mode comprises selecting at least one row of pixels for readout, disconnecting the binning circuit from the current readout circuitry, connecting a second source/drain region of the second conductivity type transistor to a predetermined voltage, disconnecting the plurality of second column lines from the ground potential, and connecting plurality of second column lines to voltage readout circuitry.