Four-bit FinFET NVRAM memory device
First Claim
Patent Images
1. A semiconductor device, comprising:
- a fin body having opposite first and second ends and opposite first and second sidewalls, said first and second sidewalls disposed between said first and second ends;
a first gate dielectric stack disposed on said first sidewall and a second gate dielectric stack disposed on said second sidewall, said first and second stacks each comprising at least a first, a second and a third dielectric layer, said first dielectric layer of said first dielectric stack in direct physical contact with said first sidewall and said first dielectric layer of said second dielectric stack in direct physical contact with said second sidewall;
a first gate electrode in direct physical contact with said third dielectric layer of said first gate dielectric stack and a second gate electrode in direct physical contact with said third dielectric layer of said second gate dielectric stack, said first and second gate electrodes not in direct physical contact with each other;
a first source/drain in said first end of said fin body and a second source/drain in said second end of said fin body; and
a channel region in said fin body between said first and second source/drains and aligned between said first and second gate electrodes.
7 Assignments
0 Petitions
Accused Products
Abstract
A four-bit FinFET memory cell, method of fabricating four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.
155 Citations
22 Claims
-
1. A semiconductor device, comprising:
-
a fin body having opposite first and second ends and opposite first and second sidewalls, said first and second sidewalls disposed between said first and second ends; a first gate dielectric stack disposed on said first sidewall and a second gate dielectric stack disposed on said second sidewall, said first and second stacks each comprising at least a first, a second and a third dielectric layer, said first dielectric layer of said first dielectric stack in direct physical contact with said first sidewall and said first dielectric layer of said second dielectric stack in direct physical contact with said second sidewall; a first gate electrode in direct physical contact with said third dielectric layer of said first gate dielectric stack and a second gate electrode in direct physical contact with said third dielectric layer of said second gate dielectric stack, said first and second gate electrodes not in direct physical contact with each other; a first source/drain in said first end of said fin body and a second source/drain in said second end of said fin body; and a channel region in said fin body between said first and second source/drains and aligned between said first and second gate electrodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An NVRAM memory, comprising:
-
an array of four-bit memory cells arranged in rows and columns, each 4-bit memory cell comprising; a fin body having opposite first and second ends and opposite first and second sidewalls, said first and second sidewalls disposed between said first and second ends; a first gate dielectric stack disposed on said first sidewall and a second gate dielectric stack disposed on said second sidewall, said first and second stacks each comprising at least a first, a second and a third dielectric layer, said first dielectric layer of said first dielectric stack in direct physical contact with said first sidewall and said first dielectric layer of said second dielectric stack in direct physical contact with said second sidewall; a first gate electrode in direct physical contact with said third dielectric layer of said first gate dielectric stack and a second gate electrode in direct physical contact with said third dielectric layer of said second gate dielectric stack, said first and second gate electrodes not in direct physical contact with each other; a first source/drain in said first end of said fin body and a second source/drain in said second end of said fin body; and a channel region in said fin body between said first and second source/drains and aligned between said first and second gate electrodes; a first wordline connected to each first gate electrode and a second wordline connected to each second gate electrode of each four-bit memory cell in a same row of four-bit memory cells of said array of four-bit memory cells; and a first bitline connected to each first source/drain and a second bitline connected to each second source/drain of each four-bit memory cell in a same column of four-bit memory cells of said array of four-bit memory cells. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
-
Specification