Semiconductor package

• US 7,091,607 B2
• Filed: 12/07/2004
• Issued: 08/15/2006
• Est. Priority Date: 03/11/2004
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liu, Sheng Tsung
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Rodela, Eduardo A.
• Application Number:
  US11/004,913
• Publication Number:
  US 20050200007A1
• Time in Patent Office: 616 Days
• Field of Search: 257/686, 257/691, 257/724, 257/777, 257/924, 257/E23.044, 257/E23.057, 361/734
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/48253 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/48265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor package includes a substrate, a chip, and at least one capacitor. The chip adheres to the substrate and has an active surface, a grounding area disposed on the active surface and at least one power pad mounted on the active surface. The capacitor is disposed on the grounding area of the chip and has a power end and a grounding end electrically connected to the grounding area. At least one bonding wire electrically connects the power end of the capacitor to the power pad.

Claims

1. A semiconductor package, comprising:

a carrier;

a chip disposed on the carrier and having an active surface, a grounding area disposed on the active surface and at least one power pad disposed on the active surface;

at least one capacitor directly disposed on the grounding area of the chip and having a power end and a grounding end electrically connected to the grounding area; and

at least one bonding wire electrically connecting the power end of the capacitor to the power pad.

2. The semiconductor package as claimed in claim 1, wherein the carrier is a substrate including a power ring surrounding the chip and a grounding ring surrounding the chip;

the semiconductor package further comprising a plurality of second and third bonding wires electrically connecting the power pad of the chip to the power ring of the substrate and electrically connecting the grounding area of the chip to the grounding ring of the substrate, respectively.

3. The semiconductor package as claimed in claim 1, wherein the carrier is a leadframe further having a plurality of first and second leads;

the semiconductor package further comprising a plurality of second and third bonding wires electrically connecting the power pad of the chip to the first lead of the leadframe and electrically connecting the grounding area of the chip to the second lead of the leadframe, respectively.

4. The semiconductor package as claimed in claim 1, further comprising a solder paste soldering the grounding end of the capacitor to the grounding area.

5. The semiconductor package as claimed in claim 4, wherein the capacitor further has a metal layer comprising Nickel and Tin, and the metal layer is disposed between the grounding end and the grounding area.

6. The semiconductor package as claimed in claim 1, further comprising a conductive adhesive electrically connecting and physically bonding the grounding end of the capacitor to the grounding area.

7. The semiconductor package as claimed in claim 1, wherein the grounding area is formed by using photolithography and etching processes of a redistribution layer.

8. The semiconductor package as claimed in claim 1, wherein the grounding area is made of electrically conductive material.

9. The semiconductor package as claimed in claim 8, wherein the grounding area is a metal sheet.

10. The semiconductor package as claimed in claim 8, wherein the grounding area is a copper layer.

11. The semiconductor package as claimed in claim 1, wherein the grounding area comprises a plurality of grounding pads and the grounding end of the capacitor is soldered to one of the grounding pads.

12. The semiconductor package as claimed in claim 1, wherein

said chip is disposed on top of said carrier and has an upper surface as said active surface;

said at least one capacitor has an upper terminal as said power end and a lower terminal as said grounding end; and

said package further comprises a conductive bonding material physically sandwiched between said lower terminal of said capacitor and the grounding area of the upper, active surface of said chip, said bonding material both physically fixing the capacitor to said upper, active surface of said chip and electrically connecting the lower terminal of said capacitor to said grounding area.

13. The semiconductor package as claimed in claim 12, further comprising multiple said capacitors disposed side by side within said grounding area which comprises a conductive material layer extending continuously underneath and physically supporting from below all said multiple capacitors.

14. The semiconductor package as claimed in claim 13, wherein the carrier is a substrate including a power ring surrounding the chip and a grounding ring surrounding the chip;

the semiconductor package further comprising a further bonding wire electrically and directly connecting said conductive material layer of the grounding area to the grounding ring of the substrate.

15. The semiconductor package as claimed in claim 14, wherein said conductive material layer has a portion which is not located underneath any of said capacitors and which is electrically connected and physically bonded to an end of said further bonding wire.

16. The semiconductor package as claimed in claim 13, wherein the carrier is a leadframe further having at least first and second leads;

the semiconductor package further comprising second and third bonding wires electrically connecting the power pad of the chip to the first lead of the leadframe and electrically and directly connecting said conductive material layer of the grounding area to the second lead of the leadframe, respectively.

17. The semiconductor package as claimed in claim 16, wherein said conductive material layer has a portion which is not located underneath any of said capacitors and on which an end of said third bonding wire lands.

18. The semiconductor package as claimed in claim 12, wherein said grounding area comprises a conductive material layer extending continuously underneath and physically supporting from below said capacitor;

said conductive material layer further extending continuously, radially outwardly beyond a boundary of said lower terminal of said capacitor to define a peripheral zone surrounding said capacitor;

said package further comprising a further bonding wire electrically connecting said conductive material layer of said grounding area to a grounding terminal of said package, said further bonding wire having an end located in said peripheral zone.

19. The semiconductor package as claimed in claim 18, wherein said grounding terminal of said package is either a grounding ring which is located on an upper surface of said carrier and surrounds the chip or a lead of a leadframe being used as said carrier.

20. The semiconductor package as claimed in claim 12, wherein said bonding wire is the only bonding wire electrically connecting the upper terminal of the capacitor to the power pad.