Multilevel copper interconnects with low-k dielectrics and air gaps

• US 7,091,611 B2
• Filed: 03/06/2002
• Issued: 08/15/2006
• Est. Priority Date: 05/31/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US10/093,244
• Publication Number:
  US 20020098677A1
• Time in Patent Office: 1,623 Days
• Field of Search: 257758-760, 257/522, 257/776, 257/276, 257/410, 438618-619, 438622-624, 438421-422, 438/626, 438/631, 438/633, 438/675, 438/680, 438/702, 438/686, 438/629, 438/411
• US Class Current: 257/758
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance.

In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material. Structures and systems are similarly included in the present invention.

Claims

1. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a number of multilayer metal lines connecting to a number of silicon devices in the substrate;

a low dielectric constant, fluorinated silica containing insulator in a number of interstices between the number of multilayer metal lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material in the number of interstices; and

wherein the air gaps are disposed between the low dielectric constant material and sidewalls of at least some of the multilayer metal lines.

2. The integrated circuit of claim 1, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

3. The integrated circuit of claim 1, wherein the number of multilayer metal lines includes a number of multilayer metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold.

4. The integrated circuit of claim 1, wherein the number of multilayer metal lines includes a first conductor bridge level.

5. The integrated circuit of claim 1, wherein a first of the number of air gaps is directly beneath a first layer of the number of multilayer metal lines and enclosed by the low dielectric constant, fluorinated insulator.

6. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a number of multilayer metal lines connecting to a number of silicon devices in the substrate;

a low dielectric constant, fluorinated silica containing insulator in a number of interstices between the number of multilayer metal lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material;

wherein the low dielectric constant insulator includes a low dielectric constant insulator having a dielectric constant of less than 2.7; and

wherein the air gaps are disposed between the low dielectric constant material and sidewalls of at least some of the multilayer metal lines.

7. The integrated circuit of claim 6, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

8. The integrated circuit of claim 6, wherein the number of multilayer metal lines includes a number of multilayer metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold.

9. The integrated circuit of claim 6, wherein the number of multilayer metal lines includes a first conductor bridge level.

10. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a number of multilayer metal lines connecting to a number of silicon devices in the substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

11. The integrated circuit of claim 10, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

12. The integrated circuit of claim 10, wherein the number of multilayer metal lines includes a number of multilayer metal lines selected from the group consisting of Aluminum, Copper, Silver, and Gold.

13. The integrated circuit of claim 10, wherein the number of multilayer metal lines includes a first conductor bridge level.

14. An integrated circuit, comprising:

a substrate including one or more transistors;

a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;

a low dielectric constant, fluorinated silica containing insulator in a number of interstices between the number of multilayer Copper lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material in the number of interstices; and

wherein the air gaps are disposed between the low dielectric constant material and sidewalls of at least some of the multilayer metal lines.

15. The integrated circuit of claim 14, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

16. An integrated circuit, comprising:

a substrate including one or more transistors;

a number of multilayer Copper lines connecting to one or more of the transistors in the substrate, wherein the number of multilayer Copper lines includes an interlayer connection;

a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material;

wherein the low dielectric constant insulator includes a low dielectric constant insulator having a dielectric constant of less than 2.7;

wherein the interlayer connection is substantially surrounded by one of the number of air gaps, which is enclosed by the low dielectric constant insulator.

17. The integrated circuit of claim 16, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

18. The integrated circuit of claim 16, wherein the number of multilayer metal lines includes a first conductor bridge level.

19. An integrated circuit, comprising:

a substrate including one or more transistors;

a number of multilayer Copper lines connecting to one or more of the transistors in the substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer Copper lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film.

20. The integrated circuit of claim 19, wherein the low dielectric constant insulator includes a low dielectric constant organic silica film.

21. The integrated circuit of claim 19, wherein the number of multilayer metal lines includes a first conductor bridge level.

22. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a number of multilayer metal lines connecting to a number of silicon devices in the substrate;

a low dielectric constant insulator in a number of interstices between the number of multilayer metal lines and the substrate;

wherein the low dielectric constant insulator includes a number of air gaps in the low dielectric constant material; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that for a content of silicon atoms in the film and has a dielectric constant of less than 2.7.

23. The integrated circuit of claim 22, wherein the number of air gaps is respectively positioned directly below one of the number of multilayer metal lines.

24. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a first layer above the substrate including a first number of metal lines, wherein one of the first number of metal lines connects to the at least one semiconductor device;

a second layer above the first layer including a second number of metal lines;

an interlayer conductor line connecting the one of the first number of metal lines to one of the second number of metal lines;

a low dielectric constant insulator material in between adjacent first number of metal lines and in between adjacent second number of metal lines;

an air gap in the low dielectric constant material adjacent the interlayer conductor separate the low dielectric constant material from portions of the interlayer conductor and between the one of the first number of metal lines and the one of the second number of metal lines; and

wherein the low dielectric constant material encloses the air gap.

25. The integrated circuit of claim 24, wherein the low dielectric constant insulator includes a low dielectric constant insulator having a dielectric constant of less than 2.7.

26. An integrated circuit, comprising:

at least one semiconductor device formed in substrate;

a first layer above the substrate including a first number of metal lines, wherein one of the first number of metal lines connects to the at least one semiconductor device;

a second layer above the first layer including a second number of metal lines;

an interlayer conductor line connecting the one of the first number of metal lines to one of the second number of metal lines;

a low dielectric constant insulator material in between adjacent first number of metal lines and in between adjacent second number of metal lines;

an air gap in the low dielectric constant material adjacent the interlayer conductor and between the one of the first number of metal lines and the one of the second number of metal lines;

wherein the low dielectric constant material encloses the air gap; and

wherein the low dielectric constant insulator includes a film in which of a set of methyl groups and a fluorine group of atoms are as much as 43% and 9% respectively of that of a content of silicon atoms in the film.

27. The integrated circuit of claim 26, wherein the interlayer conductor line intersects the air gap and is free of contact with the low dielectric constant material.