Method and apparatus for simplifying the control of a switch

• US 7,091,752 B2
• Filed: 09/30/2003
• Issued: 08/15/2006
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Balakrishnan, Balu
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US10/675,824
• Publication Number:
  US 20050068089A1
• Time in Patent Office: 1,050 Days
• Field of Search: 327108-112, 327/436, 327/437, 361/56, 361/57, 361/86, 361/87, 361 89- 913, 361/91.5
• US Class Current: 327/108
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A technique for simplifying the control of a switch is presented. In one embodiment, a method of controlling a switch as a function of the voltage across the switch is presented. In one embodiment a method of controlling a switch as a function of the slope of the voltage across the switch is present. In one embodiment a switching is switched on for an on time period that is substantially fixed in response to a voltage across the switch while the switch is off. In one embodiment a switch is switched on for an on time period that is substantially fixed in response to the slope of the voltage across the switch while the switch is off.

Claims

1. A circuit, comprising:

a high side switch to be coupled between an input and a load; and

a control circuit coupled to the high side switch, the control circuit adapted to control the high side switch as a function of a voltage across the high side switch, wherein the control circuit is adapted to turn the high side switch on for an on time period when the control circuit senses the voltage across the high side switch crosses below a first threshold while the high side switch is off.

2. The circuit of claim 1 wherein the on time period is substantially fixed.

3. The circuit of claim 1 wherein the control circuit is adapted to turn off the high side switch before an end of an on time period if the control circuit senses that the voltage drop across the high side switch crosses above a second threshold.

4. The circuit of claim 3 wherein the control circuit is adapted to turn off the high side switch for a minimum off time period before the control circuit turns the high side switch on again.

5. The circuit of claim 1 wherein the control circuit is adapted to delay the high side switch from being turned on for a delay time after the voltage across the high side switch crosses below the first threshold while the high side switch is off.

6. The circuit of claim 1 wherein the load comprises a transfonner.

7. The circuit of claim 6 wherein the transformer includes a winding, wherein the control circuit is coupled to the winding of the transformer.

8. The circuit of claim 1 wherein the high side switch is included in an integrated circuit.

9. The circuit of claim 1 wherein the circuit is included in an integrated circuit.

10. The circuit of claim 1 wherein the circuit is included in a power conversion circuit.

11. The circuit of claim 1 wherein the high side switch is a metal oxide semiconductor field effect transistor (MOSFET).

12. The circuit of claim 1 wherein the control circuit is adapted to turn the high side switch on for an on time period when the control circuit senses a change in a slope of the voltage across the high side switch over time while the high side switch is off.

13. The circuit of claim 12 wherein the on time period is substantially fixed.

14. The circuit of claim 13 wherein the change in the slope of the voltage across the high side switch over time represents a change in a polarity of the slope of the voltage across the high side switch over time.

15. The circuit of claim 12 wherein the control circuit is adapted to turn off the high side switch before an end of an on time period if the control circuit senses that the voltage drop across the high side switch crosses above a second threshold.

16. The circuit of claim 1 wherein the control circuit is adapted to keep the high side switch off for a minimum off time period following a turn off of the high side switch.

17. The circuit of claim 12 wherein the control circuit is adapted to delay the high side switch from being turned on for a delay time after the change in the slope of the voltage across the high side switch over time while the high side switch is off.

18. The circuit of claim 1 wherein the input comprises a positive input terminal and a negative input terminal, wherein the high side switch is to be coupled between the positive input terminal and the load, the circuit further comprising a low side switch to be coupled between the negative input terminal and the load.

19. The circuit of claim 18 wherein the low side switch is coupled to a second control circuit wherein the second control circuit is adapted to control the low side switch as a function of a voltage across the low side switch.

20. The circuit of claim 19 wherein the low side switch is turned on after a delay time for a low side on time period when the voltage across the low side switch crosses below a low side threshold while the low side switch is off.

21. The circuit of claim 20 wherein the delay time is substantially zero.

22. The circuit of claim 20 further comprising a feedback circuit coupled between the load and the second control circuit to provide a feedback control loop, wherein the second control circuit is adapted to vary the delay time to regulate power delivered to the load.

23. The circuit of claim 18 wherein the high side switch is turned on for a high side on time period when a voltage across the high side switch crosses below a high side threshold.

24. The circuit in claim 23 wherein the low side switch is turned on after a delay time for a low side on time period when a voltage across the low side switch crosses below a low side threshold.

25. The circuit of claim 24 wherein the high side on time period and the low side on time period are substantially fixed.

26. The circuit of claim 24 wherein the high side on time period and low side on time periods are substantially equal.

27. The circuit of claim 24 wherein the high side on time period is adjusted to maintain a voltage across the load during the high side on time period substantially equal to the voltage across the load during the low side on time period.

28. The circuit of claim 24 wherein the delay time is substantially zero.

29. The circuit of claim 18 wherein the high side switch is turned on for a high side on time period when a slope of a voltage across the high side switch changes while the high side switch is off.

30. The circuit of claim 29 wherein the low side switch is turned on after a delay time for a low side on time period when a slope of a voltage across the low side switch changes while the low side switch is off.

31. The circuit of claim 30 wherein the high side on time period and the low side on time period are substantially fixed.

32. The circuit of claim 30 wherein the change in the slope of the voltage across the high side and low side switches is a change in a polarity of the slope across the high side and low side switches.

33. The circuit of claim 30 wherein the high side on time period and low side on time periods are substantially equal.

34. The circuit of claim 30 wherein the high side on time period is adjusted to maintain a voltage across the load during the high side on time period substantially equal to the voltage across the load during the low side on time period.

35. The circuit of claim 34 wherein the voltage across the load during the high side on time period is sensed after a delay from the start of the high side on time period.

36. The circuit of claim 34 wherein the voltage across the load during the low side on time period is sensed after a delay from the start of the low side on time period.

37. The circuit of claim 30 wherein the delay time is substantially zero.

38. The circuit of claim 30 further comprising a feedback circuit coupled between the load and the second control circuit to provide a feedback control ioop, wherein the second control circuit is adapted to vary the delay time to regulate power delivered to the load.

39. The circuit of claim 30 wherein the low side switch is included in a low side integrated circuit.

40. The circuit of claim 39 wherein the low side integrated circuit further comprises the second control circuit to generate the low side on time period.

41. The circuit of claim 39 wherein the low side integrated circuit also comprises a sense circuit to sense a turn off of the high side switch.

42. The circuit of claim 41 wherein the sense circuit senses the turn off of the high side switch by monitoring the voltage across the low side switch.

43. The circuit of claim 29 wherein the high side switch is included in a high side integrated circuit.

44. The circuit of claim 43 wherein the high side integrated circuit further comprises the control circuit to generate the high side on time period.

45. The circuit of claim 44 wherein the high side integrated circuit also comprises a sense circuit to sense a turn off of the high side switch.

46. The circuit of claim 45 wherein the sense circuit senses the turn off of the low side switch by monitoring the voltage across the high side switch.

47. A half bridge circuit, comprising:

a low side switch;

a high side switch coupled to the low side switch;

a low side capacitor coupled to the low side switch;

a high side capacitor coupled to the low side capacitor and the high side switch; and

a load connected between a junction between the low side switch and high side switch and a junction between the low side capacitor and the high side capacitor, wherein the high side switch is adapted to be turned on for a high side on time period as a function of a voltage across the high side switch in response to the low side switch turning off, wherein the high side switch is adapted to be turned on for the high side on time period when the voltage across the high side switch crosses below a first threshold while the high side switch is off.

48. The half bridge circuit of claim 47 wherein the low side switch is adapted to be turned on for a low side on time period following a delay time after the high side switch is turned off as a function of a voltage across the low side switch in response to the high side switch turning off.

50. The circuit of claim 47 wherein the high side switch is adapted to be turned on for the high side on time period as a function of a slope of the voltage across the high side switch over time.

51. The half bridge circuit of claim 48 wherein one of the high side on time period or the low side on time period is adapted to be adjusted to maintain a voltage across the load during the high side on time period substantially equal to the voltage across the load during the low side on time period.

52. The half bridge circuit of claim 47 wherein the voltage across the load is sensed for a fixed period during the high side on time period.

53. The half bridge circuit of claim 48 wherein the voltage across the load is sensed for a fixed period during the low side on time period.

54. The half bridge circuit of claim 48 wherein the delay time is substantially zero.

55. The half bridge circuit of claim 48 further comprising a feedback circuit coupled between the load and the low side switch to vary the delay time to regulate power delivered to the load.

56. The half bridge circuit of claim 48 wherein the low side switch is included in a low side integrated circuit of the half bridge circuit.

57. The half bridge circuit of claim 56 wherein the low side integrated circuit also comprises a low side control circuit coupled to the low side switch to generate the low side on time period.

58. The half bridge circuit of claim 57 where the low side control circuit is coupled to sense a turn off of the high side switch.

59. The half bridge circuit of claim 58 wherein the low side control circuit is adapted to sense the turn off of the high-side switch by monitoring the voltage across the low side switch.

60. The half bridge circuit of claim 47 wherein the high side switch is included in a high side integrated circuit of the half bridge circuit.

61. The half bridge circuit of claim 60 wherein the high side integrated circuit also comprises a high side control circuit coupled to the high side switch to generate the high side on time period.

62. The half bridge circuit of claim 61 wherein the high side control circuit is coupled to sense a turn off of the low side switch.

63. The half bridge circuit of claim 62 wherein the high side control circuit is adapted to sense the turn off of the low side switch by monitoring the voltage across the high-side switch.

64. The half bridge circuit of claim 48 wherein the half bridge circuit is included in a switched mode power supply.

65. The half bridge circuit of claim 48 wherein the half bridge circuit is included in a power conversion circuit.

66. The half bridge circuit of claim 48 wherein the low side switch and the high side switch each comprise a metal oxide field effect transistor (MOSFET).

49. The circuit of 48 wherein the high side on time period and the low side on time period are substantially fixed.