Modulating ramp angle in a digital frequency locked loop

• US 7,091,795 B1
• Filed: 12/16/2005
• Issued: 08/15/2006
• Est. Priority Date: 10/09/2001
• Status: Expired due to Term

• Current Assignee: IXYS Intl Limited (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Tsyrganovich, Anatoliy V.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US11/305,291
• Time in Patent Office: 242 Days
• Field of Search: 331/1.R, 331/1.A, 331/18, 331/25, 331/DIG.2, 375/373, 375/375, 375/376, 327/105, 327/116, 327/119, 327/141, 327/144, 327/145, 327/147, 327/156, 327/160, 327/162
• US Class Current: 331/1.00R
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable both to clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. Ramp slope dithering is used to increase resolution. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Claims

1. An integrated circuit, comprising:

a terminal that receives a first clock signal of a first frequency;

a processor having a clock input lead; and

a frequency-locked-loop (FLL) circuit that receives the first clock signal from the terminal and generates therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL circuit comprises a digital filter and a ramp generator, wherein the FLL circuit locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the FLL circuit determines a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the FLL circuit determines a second digital value indicative of a second magnitude of the ramp signal, wherein the first digital value and the second digital value are used to generate a third digital value, and wherein the third digital value is supplied to the digital filter.

2. The integrated circuit of claim 1, wherein the first slope is modulated.

3. The integrated circuit of claim 1, wherein the first slope equals the second slope, and wherein the first slope and the second slope are modulated in unison.

4. The integrated circuit of claim 1, wherein the ramp generator receives a slope control signal, and wherein the first slope and the second slope are determined at least in part by the slope control signal.

5. The integrated circuit of claim 4, wherein the slope control signal is a multi-bit digital signal.

6. The integrated circuit of claim 1, wherein the third digital value is generated by subtracting the second digital value from the first digital value.

7. The integrated circuit of claim 6, wherein the first slope is increased as the third digital value approaches digital zero.

8. An integrated circuit, comprising:

a terminal;

an oscillator circuit coupled to the terminal, the oscillator circuit outputting a first clock signal of a first frequency;

a processor having a clock input lead; and

a frequency locked loop (FLL) having an input lead and an output lead, the FLL receiving the first clock signal from the oscillator circuit and generating therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL comprises a ramp generator and a comparator set, wherein the FLL locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the comparator set outputs a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the comparator set outputs a second digital value indicative of a second magnitude of the ramp signal, wherein a third digital value is generated by subtracting the second digital value from the first digital value, and wherein the first signal becomes locked to the second signal as the third digital value approaches a digital zero.

9. The integrated circuit of claim 8, wherein a real time clock receives the first clock signal.

10. The integrated circuit of claim 8, wherein the first frequency is 32,768 hertz, and wherein the second frequency is greater than 32,768 hertz.

11. The integrated circuit of claim 8, wherein the processor is programmed to change the multiple.

12. The integrated circuit of claim 8, wherein the multiple is an integer that can be programmed.

13. The integrated circuit of claim 8, wherein the integrated circuit is part of a battery-powered device, wherein the first frequency is less than 5 megahertz, and wherein the second frequency is greater than 100 megahertz.

14. The integrated circuit of claim 8, wherein the terminal is coupled to a 32,768-hertz crystal external to the integrated circuit.

15. An integrated circuit, comprising:

a terminal that receives a first clock signal of a first frequency;

a processor having a clock input lead that receives a second clock signal, wherein the second clock signal has a second frequency that is a multiple of the first frequency; and

means for generating the second clock signal from the first clock signal by locking a feedback signal to a reference signal, wherein the means generates a ramp signal that has a first slope beginning at a first edge of the feedback signal, wherein the means determines a first digital value indicative of a first magnitude of the ramp signal at a first edge of the reference signal, wherein the ramp signal has a second slope beginning at a second edge of the feedback signal, wherein the means determines a second digital value indicative of a second magnitude of the ramp signal at a second edge of the reference signal, wherein the means generates a third digital value by subtracting the second digital value from the first digital value, and wherein the means locks the feedback signal to the reference signal by adjusting the feedback clock so that the third digital value approaches a digital zero.

16. The integrated circuit of claim 15, wherein the first slope is modulated over time.

17. The integrated circuit of claim 15, wherein the means comprises a random number generator.

18. An integrated circuit, comprising:

a terminal that receives a first clock signal of a first frequency;

a processor having a clock input lead that receives a second clock signal, wherein the second clock signal has a second frequency that is a multiple of the first frequency; and

a means for locking a feedback signal to a reference signal using ramp slope dithering, wherein the means generates the second clock signal using the first clock signal, and wherein the means generates the reference signal using the first clock signal.

19. The integrated circuit of claim 18, wherein the means generates a ramp signal that has a first slope beginning at a first edge of the feedback signal, wherein the means determines a first digital value indicative of a first magnitude of the ramp signal at a first edge of the reference signal, wherein the ramp signal has a second slope beginning at a second edge of the feedback signal, wherein the means determines a second digital value indicative of a second magnitude of the ramp signal at a second edge of the reference signal, wherein the means generates a third digital value by subtracting the second digital value from the first digital value, and wherein the means locks the feedback signal to the reference signal by adjusting the feedback clock so that the third digital value approaches a digital zero.

20. The integrated circuit of claim 18, wherein the means generates a ramp signal that has a first slope beginning at a first edge of the feedback signal and a second slope beginning at a second edge of the feedback signal, wherein the first slope equals the second slope, and wherein the ramp slope dithering modulates the first slope and the second slope in unison.