Modulating ramp angle in a digital frequency locked loop
First Claim
1. An integrated circuit, comprising:
- a terminal that receives a first clock signal of a first frequency;
a processor having a clock input lead; and
a frequency-locked-loop (FLL) circuit that receives the first clock signal from the terminal and generates therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL circuit comprises a digital filter and a ramp generator, wherein the FLL circuit locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the FLL circuit determines a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the FLL circuit determines a second digital value indicative of a second magnitude of the ramp signal, wherein the first digital value and the second digital value are used to generate a third digital value, and wherein the third digital value is supplied to the digital filter.
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Accused Products
Abstract
A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable both to clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. Ramp slope dithering is used to increase resolution. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.
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Citations
20 Claims
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1. An integrated circuit, comprising:
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a terminal that receives a first clock signal of a first frequency; a processor having a clock input lead; and a frequency-locked-loop (FLL) circuit that receives the first clock signal from the terminal and generates therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL circuit comprises a digital filter and a ramp generator, wherein the FLL circuit locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the FLL circuit determines a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the FLL circuit determines a second digital value indicative of a second magnitude of the ramp signal, wherein the first digital value and the second digital value are used to generate a third digital value, and wherein the third digital value is supplied to the digital filter. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit, comprising:
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a terminal; an oscillator circuit coupled to the terminal, the oscillator circuit outputting a first clock signal of a first frequency; a processor having a clock input lead; and a frequency locked loop (FLL) having an input lead and an output lead, the FLL receiving the first clock signal from the oscillator circuit and generating therefrom a second clock signal, the second clock signal having a second frequency that is a multiple of the first frequency, wherein the second clock signal is supplied to the clock input lead of the processor, wherein the FLL comprises a ramp generator and a comparator set, wherein the FLL locks a first signal to a second signal, wherein the ramp generator generates a ramp signal that has a first slope beginning at a first edge of the first signal, wherein at a first edge of the second signal the comparator set outputs a first digital value indicative of a first magnitude of the ramp signal, wherein the ramp signal has a second slope beginning at a second edge of the first signal, wherein at a second edge of the second signal the comparator set outputs a second digital value indicative of a second magnitude of the ramp signal, wherein a third digital value is generated by subtracting the second digital value from the first digital value, and wherein the first signal becomes locked to the second signal as the third digital value approaches a digital zero. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An integrated circuit, comprising:
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a terminal that receives a first clock signal of a first frequency; a processor having a clock input lead that receives a second clock signal, wherein the second clock signal has a second frequency that is a multiple of the first frequency; and means for generating the second clock signal from the first clock signal by locking a feedback signal to a reference signal, wherein the means generates a ramp signal that has a first slope beginning at a first edge of the feedback signal, wherein the means determines a first digital value indicative of a first magnitude of the ramp signal at a first edge of the reference signal, wherein the ramp signal has a second slope beginning at a second edge of the feedback signal, wherein the means determines a second digital value indicative of a second magnitude of the ramp signal at a second edge of the reference signal, wherein the means generates a third digital value by subtracting the second digital value from the first digital value, and wherein the means locks the feedback signal to the reference signal by adjusting the feedback clock so that the third digital value approaches a digital zero. - View Dependent Claims (16, 17)
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18. An integrated circuit, comprising:
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a terminal that receives a first clock signal of a first frequency; a processor having a clock input lead that receives a second clock signal, wherein the second clock signal has a second frequency that is a multiple of the first frequency; and a means for locking a feedback signal to a reference signal using ramp slope dithering, wherein the means generates the second clock signal using the first clock signal, and wherein the means generates the reference signal using the first clock signal. - View Dependent Claims (19, 20)
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Specification