Method of fabricating silicon nitride nanodots

• US 7,092,287 B2
• Filed: 12/17/2003
• Issued: 08/15/2006
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Beulens, Jacobus Johannes, Wan, Yuet Mei
• Primary Examiner(s): Pert, Evan
• Application Number:
  US10/739,901
• Publication Number:
  US 20040224534A1
• Time in Patent Office: 972 Days
• Field of Search: 438/257, 438/260, 438/769, 438775-777, 257314-317, 365/185.01, 365/184, 977/DIG.1
• US Class Current: 365/185.01
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02329 introduction of nitrogen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: Y10S 977/72 On an electrically conducting, semi-conducting, or semi-insulating substrate

Abstract

A method of forming silicon nitride nanodots that comprises the steps of forming silicon nanodots and then nitriding the silicon nanodots by exposing them to a nitrogen containing gas. Silicon nanodots were formed by low pressure chemical vapor deposition. Nitriding of the silicon nanodots was performed by exposing them to nitrogen radicals formed in a microwave radical generator, using N₂ as the source gas.

Claims

1. A method for the formation of silicon nitride nanodots on a semiconductor substrate, the method comprising the steps of:

forming silicon nanodots on the semiconductor substrate; and

nitriding the silicon nanodots by exposing the silicon nanodots to a nitrogen containing gas.

2. The method according to claim 1, wherein the nitrogen containing gas comprises atomic nitrogen.

3. The method according to claim 1, wherein the nitrogen containing gas is provided through a remote radical generator upstream of a process chamber housing the substrate.

4. The method according to claim 3, wherein nitriding comprises providing nitrogen gas through the remote radical generator.

5. The method according to claim 1, wherein the silicon nanodots are formed using a chemical vapor deposition seed technique.

6. The method according to claim 5, wherein the chemical vapor deposition seed technique is conducted within a batch furnace.

7. The method according to claim 5, wherein the chemical vapor deposition seed technique is conducted at between about 0.001 mTorr and 1 Torr.

8. The method according to claim 7, wherein the chemical vapor deposition seed technique is conducted at between about 0.001 mTorr and 100 mTorr.

9. The method according to claim 5, wherein nitriding the silicon nanodots is conducted within a single wafer reaction chamber.

10. The method according to claim 1, wherein forming the silicon nanodots comprises forming amorphous silicon nanodots.

11. The method according to claim 10, wherein nitriding comprises maintaining the substrate below a crystallization temperature of the silicon nanodots.

12. The method according to claim 1, wherein nitriding comprises maintaining the substrate between about 300°

C. and 650°

C.

13. The method according to claim 1, wherein the silicon nanodots have an average size between about 1 nm and 100 nm.

14. The method according to claim 1, wherein the silicon nanodots have an average size between about 2 nm and 20 nm.

15. The method according to claim 1, wherein the silicon nanodots cover between about 10% and 50% of an area of the substrate surface.

16. The method according to claim 1, wherein the silicon nanodots cover between about 20% and 40% of an area of the substrate surface.

17. A method for forming a memory device, comprising:

depositing a discontinuous silicon layer on a substrate; and

nitriding the discontinuous silicon layer.

18. The method of claim 17, wherein nitriding the discontinuous silicon layer comprises exposing the discontinuous silicon layer to nitrogen radicals.

19. The method of claim 17, wherein depositing the discontinuous silicon layer comprises exposing a silicon oxide layer to a silicon containing gas.

20. The method of claim 17, wherein depositing the discontinuous silicon layer comprises forming amorphous silicon nanodots.

21. The method of claim 20, wherein the amorphous silicon nanodots have an average size between about 1 nm and 100 nm.

22. The method of claim 17, wherein depositing the discontinuous silicon layer comprises covering between about 10% and 50% of the substrate with silicon nanodots.

23. A non-volatile memory device comprising:

a semiconductor substrate;

a plurality of silicon nitride nanodots across an area of the substrate, the silicon nitride nanodots having an average size between about 1 nm and 100 nm and covering between about 10% and 50% of the area of the substrate.

24. The device of claim 23, wherein the silicon nitride nanodots have an average size between about 2 nm and 20 nm.

25. The device of claim 23, wherein the nanodots cover about 20% to 40% of the area.

26. The device of claim 23, wherein a core region of at least some of the nanodots has a lower nitrogen concentration than a surface region of the at least some of the nanodots.

27. The device of claim 23, wherein the substrate comprises a layer of silicon oxide underlying the silicon nitride nanodots.

28. An integrated circuit, comprising a substrate having a plurality of silicon nitride nanodots, wherein a core region of at least some of the nanodots has a lower nitrogen concentration than a surface region of the at least some of the nanodots.

29. The integrated circuit of claim 28, wherein the nanodots have a distribution across an area of the substrate characteristic of low pressure chemical vapor deposited silicon.

30. The integrated circuit of claim 29, wherein the nanodots have an average size between about 1 nm and 100 nm and cover between about 10% and 50% of the area of the substrate.

31. The integrated circuit of claim 30, wherein the nanodots have an average size between about 1 nm and 20 nm and cover between about 20% and 40% of the area of the substrate.

32. The integrated circuit of claim 29, further comprising a continuous dielectric layer underlying a group of the nanodots.

33. The integrated circuit of claim 32, wherein the dielectric comprises silicon oxide.