Dynamic memory and method for testing a dynamic memory

• US 7,092,303 B2
• Filed: 05/13/2002
• Issued: 08/15/2006
• Est. Priority Date: 05/22/2001
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Ohlhoff, Carsten
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/478,441
• Publication Number:
  US 20040233745A1
• Time in Patent Office: 1,555 Days
• Field of Search: 365/201, 365/222, 365/233
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders

Abstract

The invention relates to a dynamic memory having a memory cell array, a test controller to test the memory cell array and an oscillator to control the refreshing of the memory cell array. According to the invention, the memory includes a device for using the oscillator as a time base for the test controller, such that a slow time base is achieved which may be used for different self-tests of the memory.

Claims

1. A dynamic memory comprising:

a memory cell array;

a test controller to test the memory cell array, and an oscillator to control a refresh of the memory cell array, which has for a unit to utilize the oscillator as a time base for the test controller.

2. The dynamic memory as claimed in claim 1, wherein the unit comprises a counter, which counts clock cycles in an output signal of the oscillator and, after a predetermined number of clock cycles, transmits at least one interrupt to the test controller.

3. The dynamic memory as claimed in claim 2, wherein the predetermined number of clock cycles is stored in a programmable register.

4. The dynamic memory as claimed in claim 2, wherein a frequency of the oscillator is set by a programmable register.

5. The dynamic memory as claimed in claim 2, wherein the counter is designed such that one interrupt is generated.

6. The dynamic memory as claimed in claim 2, wherein the counter is designed such that an interrupt is generated when the counter reading of the counter reaches an integer multiple of the predetermined number of clock cycles.

7. The dynamic memory as claimed in claim 2, wherein the test controller is designed such that, when an interrupt arrives, it carries out a refresh operation of the memory cell array or continues an interrupted test program.

8. A method for testing a dynamic memory, which comprises a memory cell array, a test controller to test the memory cell array and an oscillator to control a refresh of the memory cell array, comprising generating at least one signal to control a test operation of the memory cell array by the test controller from the output signal of the oscillator.

9. The method as claimed in claim 8, wherein clock cycles are counted in the output signal of the oscillator and, after a predetermined number of clock cycles, at least one interrupt is generated and transmitted to the test controller.

10. The method as claimed in claim 9, wherein the predetermined number of clock cycles is set in a manner dependent on the test sequence to be carried out.

11. The method as claimed in claim 9, wherein an interrupt causes clock cycles are to be counted in the output signal of the oscillator and a further interrupt is generated when the predetermined number of clock cycles is reached.

12. The method as claimed in claim 8, wherein an interrupt in the test controller causes a refresh of the memory cell array to start or an interrupted test program is continued.

13. The method as claimed in claim 8, wherein after the arrival of a first interrupt, the test controller interrupts a test program that is running and starts a retention or bump test and, after the arrival of a second interrupt continues the interrupted test program.