Linear phase detector for high-speed clock and data recovery
First Claim
1. A phase detector for recovering data from a received data signal comprising:
- a flip-flop having a data input coupled to a data input port, and a clock input coupled to a clock port;
a latch having a data input coupled to an output of the first flip-flop, and a clock input coupled to the clock port;
a delay element having an input coupled to the data input port;
a first logic circuit having a first input coupled to the output of the flip-flop and a second input coupled to an output of the latch; and
a second logic circuit having a first input coupled to the output of the first flip-flop and a second input coupled to an output of the delay element,wherein the latch comprises;
first and second MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively;
a first clocked MOSFET having a drain terminal coupled to the source terminals of the first an second MOSFETs, a gate terminal coupled to receive a first clock signal, and a source terminal;
third and fourth MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output;
a second clocked MOSFET having a drain terminal coupled to the source of the third and fourth MOSFETs, a gate terminal coupled to receive a second clock signal, and a source terminal;
a first load including a resistive element and an inductive element connected in series and coupling the true output to a first power supply terminal;
a second load including a resistive element and an inductive element connected in series and coupling the true output to the first power supply terminal; and
a current-source MOSFET coupled between the source terminals of the first and second clocked MOSFETs and a second power supply terminal.
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Accused Products
Abstract
Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and alternating between a first level and a second level, and receiving a data signal having a first data rate, the first data rate equal to the first clock frequency. The method also includes providing a first signal by storing the data signal when the clock signal alternates from the first level to the second level, and providing a second signal by passing the first signal when the clock signal is at the first level, and storing the first signal when the clock signal is at the second level. A third signal is provided by delaying the data signal an amount of time. An error signal is provided by combining the first signal and the third signal, and a reference signal is provided by combining the first signal and the second signal.
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Citations
9 Claims
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1. A phase detector for recovering data from a received data signal comprising:
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a flip-flop having a data input coupled to a data input port, and a clock input coupled to a clock port; a latch having a data input coupled to an output of the first flip-flop, and a clock input coupled to the clock port; a delay element having an input coupled to the data input port; a first logic circuit having a first input coupled to the output of the flip-flop and a second input coupled to an output of the latch; and a second logic circuit having a first input coupled to the output of the first flip-flop and a second input coupled to an output of the delay element, wherein the latch comprises; first and second MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively; a first clocked MOSFET having a drain terminal coupled to the source terminals of the first an second MOSFETs, a gate terminal coupled to receive a first clock signal, and a source terminal; third and fourth MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output; a second clocked MOSFET having a drain terminal coupled to the source of the third and fourth MOSFETs, a gate terminal coupled to receive a second clock signal, and a source terminal; a first load including a resistive element and an inductive element connected in series and coupling the true output to a first power supply terminal; a second load including a resistive element and an inductive element connected in series and coupling the true output to the first power supply terminal; and a current-source MOSFET coupled between the source terminals of the first and second clocked MOSFETs and a second power supply terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification