Linear phase detector for high-speed clock and data recovery

• US 7,092,474 B2
• Filed: 09/18/2001
• Issued: 08/15/2006
• Est. Priority Date: 09/18/2001
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun
• Primary Examiner(s): Ha, Dac
• Assistant Examiner(s): Wong, Linda
• Application Number:
  US09/955,693
• Publication Number:
  US 20030053576A1
• Time in Patent Office: 1,792 Days
• Field of Search: 341/101, 341/100, 375/80, 375/81, 375/226, 375/239, 375/373, 359/158, 359/157, 327/159, 331/1, 369/59.2, 343/7.7
• US Class Current: 375/375
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and alternating between a first level and a second level, and receiving a data signal having a first data rate, the first data rate equal to the first clock frequency. The method also includes providing a first signal by storing the data signal when the clock signal alternates from the first level to the second level, and providing a second signal by passing the first signal when the clock signal is at the first level, and storing the first signal when the clock signal is at the second level. A third signal is provided by delaying the data signal an amount of time. An error signal is provided by combining the first signal and the third signal, and a reference signal is provided by combining the first signal and the second signal.

Claims

1. A phase detector for recovering data from a received data signal comprising:

a flip-flop having a data input coupled to a data input port, and a clock input coupled to a clock port;

a latch having a data input coupled to an output of the first flip-flop, and a clock input coupled to the clock port;

a delay element having an input coupled to the data input port;

a first logic circuit having a first input coupled to the output of the flip-flop and a second input coupled to an output of the latch; and

a second logic circuit having a first input coupled to the output of the first flip-flop and a second input coupled to an output of the delay element,

wherein the latch comprises;

first and second MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively;

a first clocked MOSFET having a drain terminal coupled to the source terminals of the first an second MOSFETs, a gate terminal coupled to receive a first clock signal, and a source terminal;

third and fourth MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output;

a second clocked MOSFET having a drain terminal coupled to the source of the third and fourth MOSFETs, a gate terminal coupled to receive a second clock signal, and a source terminal;

a first load including a resistive element and an inductive element connected in series and coupling the true output to a first power supply terminal;

a second load including a resistive element and an inductive element connected in series and coupling the true output to the first power supply terminal; and

a current-source MOSFET coupled between the source terminals of the first and second clocked MOSFETs and a second power supply terminal.

2. The phase detector of claim 1 wherein the first data input port is configured to receive a differential signal.

3. The phase detector of claim 2 wherein the first clock port is configured to receive a differential signal.

4. The phase detector of claim 3 wherein the first logic circuit and the second logic circuit are exclusive-OR gates.

5. The phase detector of claim 3 wherein the first logic circuit and the second logic circuit perform an exclusive-OR function.

6. The phase detector of claim 1 wherein the first logic circuit provides a reference signal, and the second logic circuit provides an error signal.

7. An optical receiver comprising the phase detector of claim 1.

8. An optical transceiver comprising:

an optical transmitter; and

the optical receiver of claim 7 coupled to the optical transmitter.

9. The phase detector of claim 1 wherein the flip-flop comprises:

a first clocked latch as set forth in claim 1; and

a second clocked latch as set forth in claim 1,

wherein, the gate terminals of the first and second MOSFETs in the second clocked latch respectively couple to the true output and the complementary output of the first clocked latch.