Single platform electronic tester

• US 7,092,837 B1
• Filed: 09/15/2003
• Issued: 08/15/2006
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: LTX Corp. (COHU Incorporated)
• Inventors: Hannaford, Christopher J., Rosenfeld, Eric, Blethen, Roger W., Burlison, Phillip, Perkins, Jeffrey H., Kelly, H. Neil, Terrenzi, Edward J., Menis, David, Berry, Tommie, Davis, Michael G., Curry, David W., Lanier, Kenneth J., Deome, Mark
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): SUAREZ, FELIX E
• Application Number:
  US10/663,469
• Time in Patent Office: 1,065 Days
• Field of Search: 702/66, 702/110, 702/117, 702/118, 702/121, 702/122, 702/186, 327/100, 327/105, 713/500, 714/724
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31903 tester configuration
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Claims

1. A clocking apparatus for an electronic tester, comprising:

a fixed frequency clock generator that generates a first clock;

a variable frequency clock generator that receives as an input the first clock from the fixed frequency clock generator and that generates a second clock;

a first high speed clock generator coupled to a digital pattern generator for digital testing of a device under test, wherein the first high speed clock generator receives as an input the second clock from the variable frequency clock generator and generates a third clock having a frequency that is a first multiple of a frequency of the second clock, wherein the third clock is supplied to the digital pattern generator;

a second high speed clock generator coupled to a sequenced measure system for analog testing of the device under test, wherein the second high speed clock generator receives as an input the first clock from the fixed frequency clock generator and generates a fourth clock having a frequency that is a second multiple of a frequency of the first clock, wherein the fourth clock is supplied to the sequenced measure system.

2. The clocking apparatus of claim 1, further comprising a computer that sets a frequency of the second clock of the variable frequency clock generator in response to user input with respect to the computer.

3. The clocking apparatus of claim 1, wherein the first multiple is less than one and the second multiple is greater than one.

4. The clocking apparatus of claim 1, wherein the first and second multiples are each greater than one.