Programming architecture for a programmable analog system

• US 7,092,980 B1
• Filed: 08/14/2001
• Issued: 08/15/2006
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Mar, Monte
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/929,891
• Time in Patent Office: 1,827 Days
• Field of Search: 708/3, 708/801, 708/230
• US Class Current: 708/801
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J

Abstract

A programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.

Claims

1. A multi-functional device comprising:

a bus;

a random access memory (RAM) coupled to said bus;

a central processing unit (CPU) coupled to said bus;

a plurality of analog blocks coupled to said bus, wherein said bus, RAM, CPU and analog blocks reside on a single chip, said plurality of analog blocks comprising a first set of analog blocks that is selectively and electrically couplable to and decouplable from another analog block in said plurality of analog blocks, wherein different analog functions are implemented by selectively and electrically coupling different combinations of said analog blocks; and

a plurality of configuration registers coupled to said plurality of analog blocks, wherein said analog blocks are selectively and electrically coupled according to information in said configuration registers.

2. The multi-functional device of claim 1 wherein an analog block comprises a plurality of analog elements having changeable characteristics, wherein a characteristic of an analog element is specified according to said information in said configuration registers.

3. The multi-functional device of claim 1 wherein said configuration registers are dynamically programmable.

4. The multi-functional device of claim 1 wherein inputs and outputs of each analog block are specified according to said information in said configuration registers.

5. The multi-functional device of claim 1 wherein said first set of analog blocks comprises switched capacitor blocks.

6. The multi-functional device of claim 1 wherein said first set of analog blocks comprises a first type and a second type, wherein said first type is adapted to receive a first set of inputs and wherein said second type is adapted to receive a second set of inputs different from said first set of inputs.

7. The multi-functional device of claim 1 wherein said plurality of analog blocks also comprises a second set of analog blocks, wherein said second set of analog blocks comprises continuous time blocks.

8. The multi-functional device of claim 1 comprising:

a first register bank and a second register bank coupled to said plurality of configuration registers, said first register bank and said second register bank comprising addresses for said configuration registers.

9. The multi-functional device of claim 8 wherein said first register bank is selected when a bit has a first value and said second register bank is selected when said bit has a second value.

10. An array of analog blocks comprising:

a first plurality of analog blocks comprising continuous time blocks;

a second plurality of analog blocks comprising switched capacitor blocks, said second plurality of analog blocks coupled to said first plurality of analog blocks, wherein a switched capacitor block is selectively and electrically coupled to and decoupled from another analog block to implement different analog functions and wherein said switched capacitor blocks comprise a first type and a second type wherein said first type is adapted to receive a first set of inputs and wherein said second type is adapted to receive a second set of inputs different from said first set; and

a plurality of configuration registers coupled to said first plurality and said second plurality of analog blocks, wherein said first plurality and said second plurality of analog blocks are selectively and electrically coupled in different combinations according to information in said configuration registers.

11. The array of analog blocks of claim 10 wherein an analog block comprises a plurality of analog elements having changeable characteristics, wherein a characteristic of an analog element is specified according to said information in said configuration registers.

12. The array of analog blocks of claim 10 wherein said configuration registers are dynamically programmable.

13. The array of analog blocks of claim 10 wherein inputs and outputs of each analog block are specified according to said information in said configuration registers.

14. The array of analog blocks of claim 10 wherein said configuration registers are coupled to a first register bank and a second register bank, said first register bank and said second register bank comprising addresses for said configuration registers.

15. The array of analog blocks of claim 14 wherein said first register bank is selected when a bit has a first value and said second register bank is selected when said bit has a second value.

16. A multi-functional device comprising:

a plurality of analog blocks arranged in an array having multiple columns and rows, wherein an analog block comprises a plurality of analog elements having changeable characteristics and wherein analog blocks in a column are each coupled to a digital bus; and

a configuration register coupled to said analog elements, wherein said configuration register comprises information for specifying characteristics of said analog elements and for selectively and electrically coupling said analog block to another analog block;

wherein different analog functions are implemented by changing said information in said configuration register.

17. The multi-functional device of claim 16 wherein said configuration register is dynamically programmable.

18. The multi-functional device of claim 16 wherein inputs and outputs of said analog block are specified according to information in said configuration register.

19. The multi-functional device of claim 16 wherein said analog block is a switched capacitor block.

20. The multi-functional device of claim 16 wherein said analog block is a continuous time block.

21. The multi-functional device of claim 16 wherein said configuration register is coupled to a first register bank and a second register bank, said first register bank and said second register bank comprising an addresses for said configuration register.

22. The multi-functional device of claim 21 wherein said first register bank is selected when a bit has a first value and said second register bank is selected when said bit has a second value.