Data array having redundancy messaging between array controllers over the host bus

• US 7,093,043 B2
• Filed: 12/27/2001
• Issued: 08/15/2006
• Est. Priority Date: 12/27/2001
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Tan, Choon-Seng, Pellegrino, Greg J., Labarca, Erick
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US10/034,138
• Publication Number:
  US 20030126347A1
• Time in Patent Office: 1,692 Days
• Field of Search: 710/35.1, 710305-310, 710/15, 710/8, 710/18, 710/104, 711/114, 711/162
• US Class Current: 710/104
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A data array system, and inter-controller-link messaging method, for controlling redundant access to a storage device and providing inter-controller communication without a dedicated controller link. The host has a host bus, such as a PCI bus, and the system includes an active and a standby controller that are linked to the host bus and use the host bus for an inter-controller-link. A messaging mechanism transmits messages and data over the host bus from the active to the standby controller. The standby controller includes message and data buffers for storing the messages and data written and a message queue in which the active controller writes a signal identifier indicating that a new message has been written and defining the message for processing by the standby controller (such as a message-only transfer, a partial or all data transfer, or as a data-only transfer).

Claims

1. A data array system for providing a host computer device having a host bus redundant access to a data storage device, comprising:

an active controller linked to the host bus and the data storage device, the active controller including a messaging mechanism for transmitting the messages and data over the host bus; and

a standby controller linked to the host bus and the data storage device, the standby controller including message and data buffers for storing the messages and data, whereby the host bus functions as an inter-controller-link to transfer data and controller information between the active controller and the standby controller.

2. The system of claim 1, wherein the host bus is a peripheral component interconnect (PCI) bus.

3. The system of claim 2, wherein the active and the standby controllers are PCI-compliant devices.

4. A data array system for providing a host computer device having a host bus redundant access to a data storage device, comprising:

an active controller linked to the host bus and the data storage device, the active controller including a messaging mechanism for transmitting the messages and data over the host bus; and

a standby controller linked to the host bus and due data storage device, the standby controller including message and data buffers for storing the messages and data, whereby the host bus functions as an inter-controller-link;

wherein the standby controller includes a queue for storing a signal identifier and wherein the messaging mechanism of the active controller writes the signal identifier over the host bus to the standby queue to provide processing information for the transmitted messages and data.

5. The system of claim 4, wherein standby controller includes a messaging mechanism configured to process the signal identifier in response to an interrupt from the active controller and to process the stored messages and data based on the signal identifier.

6. The system of claim 5, wherein the signal identifier indicates the stored messages and data as a message-only transfer, a message-with-data transfer, or a message-with-partial data transfer.

7. The system of claim 6, wherein the standby messaging mechanism moves data in the data buffer to memory as part of the processing of the stored messages and data.

8. The system of claim 7, wherein the active controller includes a reply queue and the standby messaging mechanism replies to the transmitted messages and data by writing a reply message to the reply queue indicating messaging can be transmitted by the active controller.

9. A method for providing inter-controller communications between an active controller and a standby controller configured for redundant communications between a host and a storage device and linked to a host bus,

comprising:

at the active controller, building a message;

with the active controller, transferring the message to the standby controller via the host bus;

with the active controller, writing to a command/reply queue at the standby controller;

with the standby controller, checking the command/reply queue for a next message; and

upon detecting the next message, processing with the standby controller the transferred message.

10. The method of claim 9, further including driving an interrupt with the active controller to standby controller and wherein the checking is performed in response to the standby controller sampling the interrupt.

11. The method of claim 10, further including with the active controller transferring data with the message, and wherein the transferred message indicates a presence or absence of the data.

12. The method of claim 11, wherein the message defines the data as all or partial and wherein the standby controller stores the data based on the all or partial data definition.

13. The method of claim 9, further including after the processing, with the standby controller writing to a reply queue at the active controller to indicate the processing is complete.

14. A data storage system with redundant data storage, comprising:

a host processor;

an active controller controlling access by the host processor to data storage devices;

a standby controller controlling access by the host processor to the data storage devices; and

a host bus communicatively linking the host processor, the active controller, and the standby controller, wherein the active and standby controllers include redundancy messaging mechanisms configured to assert and sample signals on the host bus to provide inter-controller communications over the host bus.

20. The system of claim 14, wherein the host bus is a peripheral component interconnect (PCI) bus and the active and standby controllers are PCI-compliant devices.

15. A data storage system with redundant data storage, comprising:

a host processor;

an active controller controlling access by the host processor to data storage devices;

a standby controller controlling access by the host processor to the data storage devices; and

a host bus communicatively linking the host processor, the active controller, and the standby controller, wherein the active and standby controllers include redundancy messaging mechanisms configured to assert and sample signals on the host bus to provide inter-controller communications over the host bus;

wherein the standby controller includes a command/reply queue for registering receipt of new messages and a message buffer for storing messages, and wherein the active redundancy mechanism transfers messages to the message buffer of the standby controller and writes to the command/reply queue to indicate the transmittal of the messages.

16. The system of claim 15, wherein the active redundancy mechanism asserts an interrupt to the standby controller over the host bus and the standby redundancy mechanism responds to the interrupt by checking the command/reply queue.

17. A data storage system with redundant data storage, comprising:

a host processor;

an active controller controlling access by the host processor to data storage devices;

a standby controller controlling access by the host processor to the data storage devices; and

a host bus communicatively linking the host processor, the active controller, and the standby controller, wherein the active and stand by controllers include redundancy messaging mechanisms configured to assert and sample signals on the host bus to provide inter-controller communications over the host bes;

wherein the standby controller includes a data buffer and wherein the active redundancy messaging mechanism transfers data corresponding to the message over the host bus to the data buffer.

18. The system of claim 17, wherein the standby redundancy messaging mechanism transfers the data from the data buffer to another memory device to enable receipt of additional data and transmits a signal to the active controller upon completion of the transfer of the data out of the data buffer.

19. The system of claim 18, wherein the signal includes writing to a reply queue at the active controller and transmitting an interrupt to the active controller.

21. A method for providing inter-controller communications between an active controller and a standby controller configured for redundant communications between a host and a storage device and linked to a host bus, comprising:

at the standby controller, specifying a range of memory in the standby controller as an interrupt range;

with the active controller, writing data via the host bus to the interrupt range of the standby controller; and

at the standby controller, driving a local interrupt.

22. The method of claim 21, wherein the interrupt driving is performed with a memory controller in the standby controller.

23. The method of claim 21, further including after the interrupt driving, with the standby controller writing to a reply queue at the active controller.

24. A computing device comprising:

a host central processing unit (CPU);

a host bus communicatively coupled to the host CPU;

at least one data storage device;

an active controller linked to the host bus and the at least one data storage device, the active controller including a messaging mechanism for transmitting the messages and data over the host bus; and

,

a standby controller linked to the host bus and the at least one data storage device, the standby controller including message and data buffers for storing the messages and data, whereby the host bus functions as an inter-controller-link configured to transfer data and message information between the active and standby controllers and wherein upon a failure of the active controller the inter-controller-link provides both data and message transfer within the computing device such that the host CPU can cause the standby controller to access data from the at least one data storage device.

25. A data array system for providing a host computer device having a host bus redundant access to a data storage device, comprising:

an active controller sub-system linked directly to the host bus and the data storage device, the active controller sub-system including a messaging mechanism for transmitting messages and data over the host bus; and

,

a standby controller sub-system linked directly to the host bus and the data storage device, the standby controller sub-system including message and data buffers for storing the messages and data, whereby the host bus functions as a redundant inter-controller-link to transfer data and controller information between the active controller sub-system and the standby controller sub-system, such that upon failure of either of the active controller subsystem and the standby controller sub-system the host computing device maintains access to the data storage device.