Method and apparatus for next-line prefetching from a predicted memory address

• US 7,093,077 B2
• Filed: 06/05/2002
• Issued: 08/15/2006
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jourdan, Stephan J., Cooksey, Robert N.
• Primary Examiner(s): Portka, Gary
• Assistant Examiner(s): Chery, Mardochee
• Application Number:
  US10/163,977
• Publication Number:
  US 20030105939A1
• Time in Patent Office: 1,532 Days
• Field of Search: 711/137
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions

Abstract

A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.

Claims

1. A method comprising:

receiving a cache line, the cache line including a number of address-sized words;

predicting a memory address based upon a comparison between data in the received cache line and an address of the received cache line, wherein the predicted memory address comprises one of the address-sized words of the cache line;

issuing a prefetch request for a first cache line, the first cache line corresponding to the predicted memory address; and

issuing a next-line prefetch request for a second cache line, the second cache line having a memory address contiguous with the predicted memory address.

2. The method of claim 1, further comprising scanning the first cache line for candidate memory addresses.

3. The method of claim 1, further comprising scanning the second cache line for candidate memory addresses.

4. The method of claim 1, further comprising issuing another next-line prefetch request for a cache line having a memory address contiguous with the memory address of the second cache line.

5. The method of claim 4, wherein a total number of next-line prefetch requests issued based upon the predicted memory address comprises from one to four next-line prefetch requests.

6. The method of claim 1, wherein the received cache line is associated with a demand reference stream.

7. The method of claim 1, wherein the received cache line is associated with a prefetch reference stream.

8. The method of claim 1, wherein the predicted memory address comprises a virtual address.

9. A device comprising:

a cache memory; and

a content prefetcher coupled with the cache memory, the content prefetcher to

receive a cache line, the cache line including a number of address-sized words,

predict a memory address based upon a comparison between data in the received cache line and an address of the received cache line, wherein the predicted memory address comprises one of the address-sized words of the cache line,

issue a prefetch request for a first cache line corresponding to the predicted memory address, and

issue a next-line prefetch request for a second cache line, the second cache line having a memory address contiguous with the predicted memory address.

10. The device of claim 9, the content prefetcher to scan the first cache line for candidate memory addresses.

11. The device of claim 9, the content prefetcher to scan the second cache line for candidate memory addresses.

12. The device of claim 9, the content prefetcher to issue another next-line prefetch request for a cache line having a memory address contiguous with the memory address of the second cache line.

13. The device of claim 12, wherein a total number of next-line prefetch requests issued based upon the predicted memory address comprises from one to four next-line prefetch requests.

14. The device of claim 9, wherein the received cache line is associated with a demand reference stream.

15. The device of claim 9, wherein the received cache line is associated with a prefetch reference stream.

16. The device of claim 9, wherein the predicted memory address comprises a virtual address.

17. A system comprising:

a bus;

a cache memory coupled with the bus; and

a processor coupled with the bus and the cache memory, the processor including a content prefetcher, the content prefetcher to

receive a cache line, the cache line including a number of address-sized words,

predict a memory address based upon a comparison between data in the received cache line and an address of the received cache line, wherein the predicted memory address comprises one of the address-sized words of the cache line,

issue a prefetch request for a first cache line corresponding to the predicted memory address, and

issue a next-line prefetch request for a second cache line, the second cache line having a memory address contiguous with the predicted memory address.

18. The system of claim 17, the content prefetcher to scan the first cache line for candidate memory addresses.

19. The system of claim 17, the content prefetcher to scan the second cache line for candidate memory addresses.

20. The system of claim 17, the content prefetcher to issue another next-line prefetch request for a cache line having a memory address contiguous with the memory address of the second cache line.

21. The system of claim 20, wherein a total number of next-line prefetch requests issued based upon the predicted memory address comprises from one to four next-line prefetch requests.

22. The system of claim 17, wherein the received cache line is associated with a demand reference stream.

23. The system of claim 17, wherein the received cache line is associated with a prefetch reference stream.

24. The system of claim 17, wherein the predicted memory address comprises a virtual address.

25. The system of claim 17, wherein the cache memory comprises part of the processor.

26. An article of manufacture comprising:

a medium having content that, when accessed by a device, causes the device to

receive a cache line, the cache line including a number of address-sized words;

predict a memory address based upon a comparison between data in the received cache line and an address of the received cache line, wherein the predicted memory address comprises one of the address-sized words of the cache line;

issue a prefetch request for a first cache line, the first cache line corresponding to the predicted memory address; and

issue a next-line prefetch request for a second cache line, the second cache line having a memory address contiguous with the predicted memory address.

27. The article of manufacture of claim 26, wherein the content, when accessed, further causes the device to scan the first cache line for candidate memory addresses.

28. The article of manufacture of claim 26, wherein the content, when accessed, further causes the device to scan the second cache line for candidate memory addresses.

29. The article of manufacture of claim 26, wherein the content, when accessed, further causes the device to issue another next-line prefetch request for a cache line having a memory address contiguous with the memory address of the second cache line.

30. The article of manufacture of claim 29, wherein a total number of next-line prefetch requests issued based upon the predicted memory address comprises from one to four next-line prefetch requests.

31. The article of manufacture of claim 26, wherein the received cache line is associated with a demand reference stream.

32. The article of manufacture of claim 26, wherein the received cache line is associated with a prefetch reference stream.

33. The article of manufacture of claim 26, wherein the predicted memory address comprises a virtual address.