Processing modules for computer architecture for broadband networks
First Claim
1. A computer processor comprising:
- a main memory for storing programs and data associated with said programs;
a plurality of first processing units for processing said programs and said associated data, each said first processing unit including a local memory exclusively associated with said first processing unit;
a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to direct any one of said first processing units to process one of said programs by directing the transfer of said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit and instructing said one first processing unit to initiate processing of said one program, said one first processing unit thereafter processing said one program and said data associated with said one program from said local memory exclusively associated with said one first processing unit;
wherein said main memory includes status information indicating whether the data associated with said programs currently are being processed by said first processing units.
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Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
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Citations
38 Claims
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1. A computer processor comprising:
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a main memory for storing programs and data associated with said programs; a plurality of first processing units for processing said programs and said associated data, each said first processing unit including a local memory exclusively associated with said first processing unit; a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to direct any one of said first processing units to process one of said programs by directing the transfer of said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit and instructing said one first processing unit to initiate processing of said one program, said one first processing unit thereafter processing said one program and said data associated with said one program from said local memory exclusively associated with said one first processing unit; wherein said main memory includes status information indicating whether the data associated with said programs currently are being processed by said first processing units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A processing apparatus comprising
a main memory for storing programs and data associated with said programs; -
one or more processor modules, each of said processor modules comprising a plurality of first processing units for processing said programs and said associated data, a plurality of local memories, each of said local memories being exclusively associated with a different one of said first processing units, a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to direct any one of said first processing units to process one of said programs by directing the transfer of said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit and instructing said one first processing unit to initiate processing of said one program, said one first processing unit thereafter processing said one program and said data associated with said one program from said local memory; wherein said main memory includes status information indicating whether the data associated with said programs currently are being processed by said first processing units. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification