Processing modules for computer architecture for broadband networks

• US 7,093,104 B2
• Filed: 03/22/2001
• Issued: 08/15/2006
• Est. Priority Date: 03/22/2001
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation, Toshiba Electronic Devices & Storage Corporation (Toshiba Corporation)
• Original Assignee: International Business Machines Corporation, Sony Computer Entertainment Incorporated (Sony Group Corp.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Primary Examiner(s): CHANG, JUNGWON
• Application Number:
  US09/816,752
• Publication Number:
  US 20020156993A1
• Time in Patent Office: 1,972 Days
• Field of Search: 711/5, 711/147, 711/209, 711/153, 711/163, 709/201, 709/208, 710/110, 700/3, 712/30
• US Class Current: 712/30
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

Claims

1. A computer processor comprising:

a main memory for storing programs and data associated with said programs;

a plurality of first processing units for processing said programs and said associated data, each said first processing unit including a local memory exclusively associated with said first processing unit;

a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to direct any one of said first processing units to process one of said programs by directing the transfer of said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit and instructing said one first processing unit to initiate processing of said one program, said one first processing unit thereafter processing said one program and said data associated with said one program from said local memory exclusively associated with said one first processing unit;

wherein said main memory includes status information indicating whether the data associated with said programs currently are being processed by said first processing units.

2. The processor of claim 1, wherein said main memory is a dynamic random access memory.

3. The processor of claim 1, wherein said main memory includes a plurality of memory locations, each said memory location including a memory segment exclusively associated with said memory location.

4. The processor of claim 3, wherein each said memory segment stores said status information and wherein said status information indicates the status of data stored in said memory segment'"'"'s associated memory location, the identity of a first processing unit and a memory address.

5. The processor of claim 4, wherein said status information indicates the validity of said data stored in said memory segment'"'"'s associated memory location, said identity indicates the identity of a particular one of said first processing units and said memory address indicates a storage location within the local memory exclusively associated with said particular one first processing unit.

6. The processor of claim 1, wherein each of said first processing units is a single instruction multiple data processor.

7. The processor of claim 1, wherein each of said first processing units includes a set of registers, a plurality of floating points units, and one or more buses connecting said set of registers to said plurality of floating point units.

8. The processor of claim 7, wherein each of said first processing units further includes a plurality of integer units and one or more buses connecting said plurality of integer units to said set of registers.

9. The processor of claim 1, further comprising an optical interface and an optical waveguide, said optical interface being operable to convert electrical signals generated by said processor to optical signals for transmission from said processor and to convert optical signals transmitted to said processor to electrical signals, said optical waveguide being connected to said optical interface for transmitting said optical signals.

10. The processor of claim 1, wherein said local memories are static random access memories.

11. The processor of claim 1, further comprising a rendering engine for generating pixel data, a frame buffer for temporarily storing said pixel data and a display controller for converting said pixel data to a video signal.

12. The processor of claim 1, wherein the data associated with said one program includes a stack frame.

13. The processor of claim 1, wherein each said first processing unit comprises a controller for directing, during said processing of said programs and said associated data, a transfer of further data from said main memory to the local memory exclusively associated with said first processing unit.

14. The processor of claim 1, wherein said main memory comprises a plurality of memory bank controllers and a cross-bar switch for providing a connection between each of said first processing units and said main memory.

15. The processor of claim 1, further comprising means for prohibiting each said first processing unit from reading data from, or writing data to, any of said local memories with which said first processing unit is not exclusively associated.

16. The processor of claim 1, further comprising a direct memory access controller.

17. The processor of claim 16, wherein said second processing unit directs said transfer of said one program and said data associated with said one program to the local memory exclusively associated with said one first processing unit by issuing a command to said direct memory access controller and, in response to said command, said direct memory access controller transfers said one program to the local memory exclusively associated with said one first processing unit.

18. The processor of claim 17, wherein said one first processing unit directs the transfer of further data for processing said one program from said main memory to the local memory exclusively associated with said one first processing unit by issuing a command to said direct memory access controller and, in response to said command, said direct memory access controller transfers said further data to the local memory exclusively associated with said one first processing unit.

19. The processor of claim 18, wherein said one first processing unit directs a transfer of data resulting from said processing of said one program from the local memory exclusively associated with said one first processing unit to said main memory by issuing a command to said direct memory access controller and, in response to said command, said direct memory access controller transfers said resulting data from the local memory exclusively associated with said one processing unit to said main memory.

20. A processing apparatus comprising

a main memory for storing programs and data associated with said programs;

one or more processor modules, each of said processor modules comprising a plurality of first processing units for processing said programs and said associated data, a plurality of local memories, each of said local memories being exclusively associated with a different one of said first processing units, a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to direct any one of said first processing units to process one of said programs by directing the transfer of said one program and data associated with said one program from said main memory to the local memory exclusively associated with said one first processing unit and instructing said one first processing unit to initiate processing of said one program, said one first processing unit thereafter processing said one program and said data associated with said one program from said local memory;

wherein said main memory includes status information indicating whether the data associated with said programs currently are being processed by said first processing units.

21. The processing apparatus of claim 20, wherein the number of said plurality of first processing units for at least one of said processor modules is eight.

22. The processing apparatus of claim 20, wherein the number of said first processing units for at least one of said processor modules is four.

23. The processing apparatus of claim 20, wherein each of said processor modules comprises only one said second processing unit.

24. The processing apparatus of claim 20, wherein each of said processor modules further comprises a direct memory access controller, said direct memory access controller being responsive to commands from said first processing units and said second processing unit to effect transfers of said programs and said associated data between said main memory and said local memories.

25. The processing apparatus of claim 20, wherein each of said processor modules further comprises a local bus for providing communications among said first processing units and said second processing unit.

26. The processing apparatus of claim 20, further comprising a module bus for providing communications among said processor modules.

27. The processing apparatus of claim 20, further comprising a memory bus for providing communications between each of said processor modules and said main memory.

28. The processing apparatus of claim 27, wherein said memory bus comprises a plurality of memory bank controllers and a cross-bar switch for providing a connection between each of said processor modules and said main memory.

29. The processing apparatus of claim 28, further comprising a second cross-bar switch for providing a connection between said main memory and devices external to said processing apparatus.

30. The processing apparatus of claim 28, wherein said main memory comprises a plurality of banks and each of said memory bank controllers controls accesses to a different group of said banks.

31. The processing apparatus of claim 30, wherein the number of said banks is sixty-four.

32. The processing apparatus of claim 20, wherein each of said first processing units comprises a plurality of floating point units and a plurality of integer units.

33. The processing apparatus of claim 20, further comprising one or more optical interfaces, each of said optical interfaces being operable to convert electrical signals from said processor modules to optical signals for transmission from said processing apparatus and for converting optical signals transmitted to said processing apparatus to electrical signals.

34. The processing apparatus of claim 20, wherein at least one of said processor modules further comprises a rendering engine for generating pixel data, a frame buffer for temporarily storing said pixel data and a display controller for converting said pixel data to a video signal.

35. The processing apparatus of claim 20, wherein the number of said processor modules is one.

36. The processing apparatus of claim 20, wherein the number of said processor modules is two.

37. The processing apparatus of claim 20, wherein the number of said processor modules is four.

38. The processing apparatus of claim 20, wherein the number of said processor modules is eight.